A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

Luo, Xiaorong; Zhang, Bo; Li, Zhaoji

doi:10.1016/j.sse.2007.01.034

Cited by 79 publications

(30 citation statements)

References 15 publications

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“…Some structures are proposed to break through the limitation. A very effective method is enhanced dielectric layer field (ENDIF), such as ultrathin SOI, Variable-k SOI, Shield-Trench SOI (ST SOI) and Double-Sided Trench SOI and so on [1,2,3,4]. In these devices, the electric field in the drain buried oxide (BOX) layer is enhanced greatly and breakdown voltage (BV) is mainly supported by the BOX under the drain.…”

Section: Introductionmentioning

confidence: 99%

High voltage (>1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field

Yang

Cai

et al. 2013

IEICE Electron. Express

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Abstract:A high voltage silicon-on-insulator (SOI) LDMOS with an accumulated charges layer (ACL) for double enhanced dielectric electric field (DEDF) is proposed. The electrons and holes can be accumulated in the ACL with a back-gate bias in off-state. These charges can enhance the dielectric field in the buried oxide (BOX) layer under the source and drain for improving breakdown voltage (BV). Moreover, the ACL can also enhance the reduced surface field (RESURF) effect. Compared with the conventional SOI and Shield-Trench SOI, BV of the DEDF SOI can achieve 1163 V at 1 μm BOX and 550 V back-gate voltage.

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Section: Introductionmentioning

confidence: 99%

High voltage (>1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field

Yang

Cai

et al. 2013

IEICE Electron. Express

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“…However, breakdown voltage of SOI (siliconon-insulator) is very difficult to achieve over 600 V due to limitation of vertical breakdown voltage. To enhance the vertical breakdown voltage, effective methods have been proposed, such as ENDIF (enhanced dielectric layer field) [1][2][3][4] and PSOI (Partial SOI) [5], [6]. In fact, breakdown voltage of SOI can profit from a positive back-gate voltage without enhancing the vertical breakdown voltage.…”

Section: Introductionmentioning

confidence: 99%

A new back-gate SOI high voltage device with a compound layer

Yang

Zhang

Luo

et al. 2009

2009 International Conference on Applied Superconductivity and Electromagnetic Devices

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A back-gate silicon on insulator (SOI) high voltage device with a compound layer (BG CL SOI-LDMOS) is proposed to enhance breakdown voltage of SOI device. Introducing of compound layer(CL) can effectively suppress gain of surface electric field at source side and increase electric field in the buried oxide layer. Thus breakdown voltage of device is increased remarkably with invariable specific on-resistance. The breakdown voltage and electric field profile are researched for the new structure by using 2D MEDICI software. Simulation result shows that BG CL SOI-LDMOS can reach 557 V, 165.8 % higher than conventional SOI, at 1 m-thick buried oxide layer 40 m-length drift region and 240V back-gate voltage. Keywords-silicon on insulator; breakdown voltage; compound layer I. INTRODUCTIONPower devices fabricated on silicon-on-insulator (SOI) substrate have many attractive virtues, such as ideal dielectric isolation, low leakage current near ideal isolation and high switching speed. However, breakdown voltage of SOI (siliconon-insulator) is very difficult to achieve over 600 V due to limitation of vertical breakdown voltage. To enhance the vertical breakdown voltage, effective methods have been proposed, such as ENDIF (enhanced dielectric layer field) [1][2][3][4] and PSOI (Partial SOI) [5], [6]. In fact, breakdown voltage of SOI can profit from a positive back-gate voltage without enhancing the vertical breakdown voltage. However, a large positive back-gate voltage reduces the RESURF effect and results in increasing the on-resistance and decreasing drastically breakdown voltage [7].

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“…It has been reported that the low-k dielectric buried layer [3] having low dielectric constant can reduce the horizontal drain field and the drain-substrate capacitance, and increase the breakdown voltage as a result.…”

Section: Introductionmentioning

confidence: 99%

“…The proposed device may be novel structure in RF LDMOS power devices employing partial buried insulating layer (PBlL) [3,4] and n-buried-PBlL(N+PBlL) . Higher breakdown voltage is achieved in proposed structure than conventional ones, because buried insulating layer reduces the vertical electric field near the drain junction efficiently [5].…”

Section: Introductionmentioning

confidence: 99%

The improving characteristics for RF LDMOS with insulating layer

Zhang

et al. 2009

2009 International Conference on Communications, Circuits and Systems

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A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

Cited by 79 publications

References 15 publications

High voltage (>1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field

High voltage (>1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field

A new back-gate SOI high voltage device with a compound layer

The improving characteristics for RF LDMOS with insulating layer

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