High voltage (&gt;1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field

Yang, Xiaoming; Li, Tianqian; Cai, Yu; Wang, Jun; Chen, Changjiang

doi:10.1587/elex.10.20130057

Cited by 4 publications

(1 citation statement)

References 6 publications

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“…The main static performance indexes for LDMOSFET (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor) are the breakdown voltage (BV) and the specific on-resistance (R s,on ) [1,2,3]. The REBULF (REduced BULk Field) concept has been introduced to increase the BV of LDMOS [4,5].…”

Section: Introductionmentioning

confidence: 99%

The influence of the N+ floating layer on the drift doping of RESURF LDMOS and its analytical model

Wang

et al. 2016

IEICE Electron. Express

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The influence of the N + floating layer on the drift doping of RESURF LDMOS is studied in this paper. By optimizing the electric field distribution, a new RESURF criterion for LDMOS with N + floating layer is developed as: N D t S ≤ 0.83 × 10 12 cm −2 (N D and t S are the drift doping and thickness, respectively). The optimal drift doping is smaller than that of Single RESURF LDMOS (N D t S ≤ 1.4 × 10 12 cm −2 ). Both analytical and numerical results show the N + floating layer can be used to increase the breakdown voltage of LDMOS but at the cost of a low drift doping and a large on-resistance. The effect of the N + floating layer on REBULF LDMOS is also studied in some detail. This model can be used in the design of RESURF and REBULF LDMOS to optimize the doping concentration of the drift region.

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Section: Introductionmentioning

confidence: 99%

The influence of the N+ floating layer on the drift doping of RESURF LDMOS and its analytical model

Wang

et al. 2016

IEICE Electron. Express

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Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage

Yang

Cao

et al. 2020

IEEE Access

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With two-dimensional device simulation software, the influence of the deep depletion (DD) of the silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) device substrate on the transient breakdown voltage (TrBV) was analyzed. Based on the changes in the characteristics of the charge distribution and the depletion layer in the device substrate with time and the related parameters in the off state, the mechanism of their action on the transverse and vertical breakdown voltages (BVs) was studied. TrBV demonstrates completely different characteristics from the static breakdown voltage (StBV) due to the DD effect of SOI LDMOSs. Low drift region concentration (Nd) and substrate doping concentration (Psub) are conducive to obtaining a high maximum TrBV. With increasing drain voltage (Vd), the turn-off nonbreakdown time (Tnonbv) of the device with higher Psub decreases faster. However, the Tnonbv with higher Psub is higher at low Vd. Therefore, the maximum Tnonbv can be obtained by optimizing Nd and Psub under a given Vd. In addition, Tnonbv is greatly reduced with increasing temperature.INDEX TERMS Silicon-on-insulator (SOI), MOS devices, deep depletion (DD), breakdown voltage (BV).

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Improve the Dynamic Breakdown Voltage of SOI LDMOS Devices by Eliminating the Effect of Deep Depletion in Substrate

Cai¹

2021

2021 3rd Asia Energy and Electrical Engineering Symposium (AEEES)

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High voltage (>1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field

Cited by 4 publications

References 6 publications

The influence of the <i>N</i><sup>+</sup> floating layer on the drift doping of RESURF LDMOS and its analytical model

The influence of the <i>N</i><sup>+</sup> floating layer on the drift doping of RESURF LDMOS and its analytical model

Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage

Improve the Dynamic Breakdown Voltage of SOI LDMOS Devices by Eliminating the Effect of Deep Depletion in Substrate

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