Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage

Abstract

With two-dimensional device simulation software, the influence of the deep depletion (DD) of the silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) device substrate on the transient breakdown voltage (TrBV) was analyzed. Based on the changes in the characteristics of the charge distribution and the depletion layer in the device substrate with time and the related parameters in the off state, the mechanism of their action on the transverse and vertical breakdown voltages (BVs) was studied. TrBV demonstrates completely different characteristics from the static breakdown voltage (StBV) due to the DD effect of SOI LDMOSs. Low drift region concentration (Nd) and substrate doping concentration (Psub) are conducive to obtaining a high maximum TrBV. With increasing drain voltage (Vd), the turn-off nonbreakdown time (Tnonbv) of the device with higher Psub decreases faster. However, the Tnonbv with higher Psub is higher at low Vd. Therefore, the maximum Tnonbv can be obtained by optimizing Nd and Psub under a given Vd. In addition, Tnonbv is greatly reduced with increasing temperature.INDEX TERMS Silicon-on-insulator (SOI), MOS devices, deep depletion (DD), breakdown voltage (BV).

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

“…If V d is greater than or equal to StBV, the device can be broken down after being in the off-state for a period of time. T nonbv serves as a reference for the lowest operating frequency of the device [31]. Figure 7 shows the effect of different Ts and V d s on T nonbv .…”

“…The other parameters of this device were the same as in SOI LDMOS. Figure 1 shows the circuit used to simulate the TrBV of the device [31]. The source and substrate electrodes of the test device were grounded, gate voltage V g was applied to the gate through the gate resistor R g , and a fixed drain voltage V d was applied to the drain through the drain resistor R d .…”

“…Like StBV, TrBV is determined by the smaller of the lateral breakdown voltage (BV lat ) and the vertical breakdown voltage (BV ver ). Studies have shown that although reducing the P sub can promote expansion of the depletion layer and increase BV ver , the surface field (RESURF) effect is reduced [31]. An extremely low P sub can lead to an increase in the surface electric field at the source and premature breakdown, thus reducing BV lat and resulting in a substantial decrease in TrBV [31].…”

“…Studies have shown that although reducing the P sub can promote expansion of the depletion layer and increase BV ver , the surface field (RESURF) effect is reduced [31]. An extremely low P sub can lead to an increase in the surface electric field at the source and premature breakdown, thus reducing BV lat and resulting in a substantial decrease in TrBV [31]. Therefore, the doping concentration in the drift region (N d ) needs to be reduced simultaneously to obtain high TrBV [31], whereby R on,sp is also considerably increased.…”

“…An extremely low P sub can lead to an increase in the surface electric field at the source and premature breakdown, thus reducing BV lat and resulting in a substantial decrease in TrBV [31]. Therefore, the doping concentration in the drift region (N d ) needs to be reduced simultaneously to obtain high TrBV [31], whereby R on,sp is also considerably increased. Double RESURF, step doping in the drift region, and linear variable doping in the drift region techniques are commonly applied to improve BV lat of SOI LDMOS devices [32][33][34][35].…”