&amp;#215;pipes Lite: A Synthesis Oriented Design Library For Networks on Chips

Stergiou, Stergios; Angiolini, Federico; Carta, Salvatore; Raffo, Luigi; Bertozzi, Davide; Micheli, Giovanni De

doi:10.1109/date.2005.1

Cited by 113 publications

(91 citation statements)

References 18 publications

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“…The power consumption of the NoCs is estimated by the synthesis tool that uses the power models of the components from the library in [24]. We show the breakdown of the power consumption in Figure 4.…”

Section: Power Analysismentioning

confidence: 99%

“…We use NoC switches and Network Interfaces (NIs) similar to those from [24]. We use input buffering, on/off flow control and source routing for the switches with no virtual channels.…”

Section: System Architecturementioning

confidence: 99%

“…All the topologies have 4 switches for the request network and 4 switches on the response network. We chose these topologies as they were the [24] in 65nm technology. We analyze three designs.…”

Section: System Architecturementioning

confidence: 99%

See 2 more Smart Citations

A DRAM Centric NoC Architecture and Topology Design Approach

Seiculescu

Murali

Benini

et al. 2011

2011 IEEE Computer Society Annual Symposium on VLSI

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Section: Power Analysismentioning

confidence: 99%

“…We use NoC switches and Network Interfaces (NIs) similar to those from [24]. We use input buffering, on/off flow control and source routing for the switches with no virtual channels.…”

Section: System Architecturementioning

confidence: 99%

See 1 more Smart Citation

A DRAM Centric NoC Architecture and Topology Design Approach

Seiculescu

Murali

Benini

et al. 2011

2011 IEEE Computer Society Annual Symposium on VLSI

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“…The MULT SoC consists of fifteen processor/hardware cores, ten private memories for the different processors and five shared slave devices. The regular topology is a 5 × 3 mesh, which is hand-designed to suit the application characteristics of the benchmark (presented in Figure 3(a)) [9]. The second topology is an application-specific custom topology obtained from the SUNFLOOR tool (presented in Figure 3(b)).…”

Section: A Experiments On the Multimedia Benchmarkmentioning

confidence: 99%

“…In the second step, another custom tool ×pipesCompiler [30], reads the topology definition file generated by SUNFLOOR and instantiates the RTL description of the NoC components using ×pipes [9], a pre-designed SystemC RTL component library. The modules in the component library support a large number of instantiation parameters, such as different input/output ports, buffer sizes, etc.…”

Section: • Step 2: Topology Instantiationmentioning

confidence: 99%

Routing Aware Switch Hardware Customization for Networks on Chips

Meloni

Murali

Carta

et al. 2006

2006 1st International Conference on Nano-Networks and Workshops

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Abstract-Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the evergrowing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC with low hardware overhead, matching the application requirements are essential. In this work, we present a method for reducing the hardware complexity of the NoC by automatically configuring the architecture of the NoC switches to suit the application traffic characteristics. The crossbar matrix and the arbiters of each switch in the NoC design are customized to support the traffic flows utilizing that switch. This applicationspecific switch customization is integrated with an existing design flow, which automates NoC topology synthesis, mapping, RTL code and physical layout generation. Several experimental studies on NoC benchmark designs are carried out, which show that the proposed switch customization technique leads to large reduction in the NoC switch area (28% on average) and power consumption (21% on average). Moreover, the critical paths of the switches reduce significantly, thereby leading to a significant speed-up of the NoC design.

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Capturing the sensitivity of optical network quality metrics to its network interface parameters

Ortín-Obón

Ramini

Viñals

et al. 2014

Concurrency and Computation

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Optical networks-on-chip (ONoCs) are gaining momentum as a way to improve energy consumption and bandwidth scalability in the next generation multi-core and many-core systems. Although many valuable research works have investigated their properties, the vast majority of them lacks an accurate exploration of the network interface architecture required to support optical communications on the silicon chip. The complexity of this architecture is especially critical for a specific kind of ONoCs: the wavelength-routed ones. These are capable of delivering contention-free all-to-all connectivity without the need for path reservation, unlike space-routed ONoCs. From a logical viewpoint, they can be considered as full non-blocking crossbars; thus, the control complexity is implemented at network interfaces. To our knowledge, this paper proposes the first complete network interface architecture for wavelength-routed optical NoCs, by coping with the intricacy of networking issues such as flow control, buffering strategy, deadlock avoidance, serialization, and above all, their codesign in a complete architecture. The evaluation methodology spans from area and energy analysis via actual synthesis runs in 40-nm technology to RTL-equivalent (register-transfer level) SystemC modelling of the network architecture, and aims at verifying whether the projected benefits of ONoCs versus their electrical counterparts are still preserved when the overhead of their network interface is considered in the analysis

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×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips

Cited by 113 publications

References 18 publications

A DRAM Centric NoC Architecture and Topology Design Approach

A DRAM Centric NoC Architecture and Topology Design Approach

Routing Aware Switch Hardware Customization for Networks on Chips

Capturing the sensitivity of optical network quality metrics to its network interface parameters

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