Routing Aware Switch Hardware Customization for Networks on Chips

Meloni, Paolo; Murali, Srinivasan; Carta, Salvatore; Camplani, Massimo; Raffo, Luigi; Micheli, G. De

doi:10.1109/nanonet.2006.346217

Cited by 10 publications

(9 citation statements)

References 24 publications

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“…Some researches [9][10][11] show that irregular mesh networks are more beneficial to some embedded systems than regular ones. Some typical topologies of irregular mesh are shown as Figure 2.…”

Section: Figure 1 Mesh 4*4 Topologymentioning

confidence: 99%

A New Static Data Flow Clustering Algorithm for Task Scheduling of Irregular Mesh in NoCs Based on Complex Networks

Liu¹,

Cao²,

Kong³

2016

IJFGCN

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Section: Figure 1 Mesh 4*4 Topologymentioning

confidence: 99%

A New Static Data Flow Clustering Algorithm for Task Scheduling of Irregular Mesh in NoCs Based on Complex Networks

Liu¹,

Cao²,

Kong³

2016

IJFGCN

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“…This means the intra-router resources in our NoC can be customised, while each router in [8] is not customised. In [9], an individually customised switch for NoCs is presented. In [9], parameters are specified for an individual multiplexer instance and an arbiter instance.…”

Section: Related Workmentioning

confidence: 99%

“…In [9], an individually customised switch for NoCs is presented. In [9], parameters are specified for an individual multiplexer instance and an arbiter instance. Our work is similar to [9] in that on-demand topology is configured for a switch module.…”

Section: Related Workmentioning

confidence: 99%

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

Hur

Stefanov

Wong

et al. 2012

IET Comput. Digit. Tech.

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Conventional rigid and generalpurpose on-chip networks occupy significant logic and wire resources in fieldprogrammable gate arrays (FPGAs). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors present a design of a customised crossbar switch, where physical topologies are identical to logical topologies for a given application. A multiprocessor system combined with the presented custom crossbar has been designed with the ESPAM design environment and prototyped in the FPGA device. Experiments with practical applications show that the custom crossbar occupies significantly less area, maintains higher performance and reduces the power consumption, when compared with the general-purpose crossbars. In addition, the authors present that configuration performance and cost can be improved by reducing the functional area cost in FPGAs. Second, a customisation technique for the circuit-switched network-on-chip (NoC) is presented, where only necessary half-duplex interconnects are established for a given application mapping. The presented customised NoC is implemented in FPGA and results indicate that the area is reduced by 66%, when compared with the general-purpose networks.

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“…Additionally, an input core graph, obtained with the SUNMAP tool, is used in the mapping phase [8]. Then, the SUNFLOOR tool is used to synthesize the most power and performance efficient NoC topology that satisfies the application requirements [9].…”

Section: Related Workmentioning

confidence: 99%

A simplified executable model to evaluate latency and throughput of networks-on-chip

Ost

Moraes

Möller

et al. 2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

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This paper proposes a technique that mixes simulation and an analytical method to evaluate the characteristics of Networks-onChips (NoCs). The advantage of this technique is to reduce the simulation time by reducing the complexity of the NoC model while still obtaining accurate results for latency and throughput. The basis of this technique is: (i) to send the whole payload data at once in the packet header; (ii) to reduce the NoC simulation complexity by omitting the flit by flit payload forwarding; (iii) to use an algorithm for controlling the release of the packet trailer in order to close the connection at the right time. For the evaluation of this technique, an actor-oriented model of a NoC, JOSELITO, was created. Simulation results show that JOSELITO is in average 2.3 times faster in 88% of the executed case studies than the implementation without using the proposed technique. The worst case simulation results for latency and throughput have, respectively, 5.26% and 0.1% error compared to the corresponding Register Transfer Level (RTL) model.

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Routing Aware Switch Hardware Customization for Networks on Chips

Cited by 10 publications

References 24 publications

A New Static Data Flow Clustering Algorithm for Task Scheduling of Irregular Mesh in NoCs Based on Complex Networks

A New Static Data Flow Clustering Algorithm for Task Scheduling of Irregular Mesh in NoCs Based on Complex Networks

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

A simplified executable model to evaluate latency and throughput of networks-on-chip

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