Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

Hur, Jae Young; Stefanov, Todor; Wong, Stephan; Goossens, Kees

doi:10.1049/iet-cdt.2010.0105

Cited by 11 publications

(2 citation statements)

References 26 publications

(23 reference statements)

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“…In recent years, some efficient interconnect architectures dedicated for a hardware fabric have been proposed to exploit the advantages of the fabric such as DESA NoC [Roca et al, 2012] or low-cost and specific-application crossbar in [Hur et al, 2012;Murali et al, 2007] developed for FPGAs. Additionally, many hybrid interconnects both in mixed NoC topologies and in mixed architectures have been proposed to improve the hybrid interconnect throughput or reduce hardware cost as presented in Section 2.2.…”

Section: Hardware Level Optimizationmentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

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Section: Hardware Level Optimizationmentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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“…Conventional rigid and general purpose on-chip network occupy significant logic and wire resources in Field Programmable Gate Arrays (FPGAs) [7]. To reduce the area cost, the authors presented a topology customization technique that interconnects the on-demand network which is systematically established in reconfigurable hardware.…”

mentioning

confidence: 99%

FPGA SoC Based Multichannel Data Acquisition System with Network Control Module

Rajasekaran¹,

Jeyabharath²,

Veena³

2017

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Normally, Data acquisition (DAQ) is used to acquire the signals from different devices like sensors, transducers, actuators etc. The data acquisition is also used to analyze the signals, digitizing the signals and acquiring the signals from different inputs. The main drawbacks in data acquisition system are data storage, hardware size and remote monitoring. The System-on-Chip Field Programmable Gate Array (SoC-FPGA) is used in the proposed system in the aim to reduce the hardware and memory size. Further to provide remote monitoring with Ethernet/Wi-Fi, the Network Control Module (NCM) is integrated with Data acquisition and processing module for the communication between the systems. This developed system achieves high resolution with memory reduction, reduced hardware size, fast remote monitoring and control. It is used for real time processing in DAQ and signal processing. For fault tolerance and portability, the full system reconfigurability based FPGA acts as the best solution and the system can be reused with different configurations. The control of data acquisition and the subsequent management of data are coded in LabVIEW. LabVIEW tool is used to design and develop a fourchannel Data Acquisition and Processing (DAQP) unit. National Instruments Data Acquisition (NIDAQ) and National Instruments Field Programmable Gate Array (NIFPGA) are used to test and implement the design for real time processing. This is designed to provide high accuracy, storage and portability.

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Design automation for application-specific on-chip interconnects: A survey

Cilardo

Fusella

2016

Integration

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Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

Cited by 11 publications

References 26 publications

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

FPGA SoC Based Multichannel Data Acquisition System with Network Control Module

Design automation for application-specific on-chip interconnects: A survey

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