A DRAM Centric NoC Architecture and Topology Design Approach

Abstract

Most communication traffic in today's System on Chips

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

“…Several customized irregular topologies can also be found in the literature [7][8][9]. Reconfigurability and reusability is the advantage of our work over them.…”

“…Regular topologies (like meshes) are reusable; they can be designed and optimized once and then be used in many systems. Fully customized irregular topologies [7][8][9], on the other hand, can achieve superior performance, but at the expense of altering the regularity of standard topologies and losing NoC Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/vlsi reusability. The proposed NoC architecture benefits from the advantages of regular mesh topology, as well as the superior performance of customized topologies.…”

Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems

“…Other related work that focus on improving the averagecase performance of the clients include a memory-centric NoC design that explores the benefits of a dedicated NoC for shared DRAM access by funneling the traffic from different clients to the memory with the right width converters [24]. A connectionless NoC for shared memory access with a binary arbitration tree that multiplexes multiple clients to one bus master are proven to reduce average latency and hardware cost as opposed to a connection-oriented NoC [25].…”