Capturing the sensitivity of optical network quality metrics to its network interface parameters

Abstract

Optical networks-on-chip (ONoCs) are gaining momentum as a way to improve energy consumption and bandwidth scalability in the next generation multi-core and many-core systems. Although many valuable research works have investigated their properties, the vast majority of them lacks an accurate exploration of the network interface architecture required to support optical communications on the silicon chip. The complexity of this architecture is especially critical for a specific kind of ONoCs: the wavelength-routed ones. These are capable of delivering contention-free all-to-all connectivity without the need for path reservation, unlike space-routed ONoCs. From a logical viewpoint, they can be considered as full non-blocking crossbars; thus, the control complexity is implemented at network interfaces. To our knowledge, this paper proposes the first complete network interface architecture for wavelength-routed optical NoCs, by coping with the intricacy of networking issues such as flow control, buffering strategy, deadlock avoidance, serialization, and above all, their codesign in a complete architecture. The evaluation methodology spans from area and energy analysis via actual synthesis runs in 40-nm technology to RTL-equivalent (register-transfer level) SystemC modelling of the network architecture, and aims at verifying whether the projected benefits of ONoCs versus their electrical counterparts are still preserved when the overhead of their network interface is considered in the analysis

Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

“…For the complete ENI architecture, the interested reader is referred to [36]. We obtained the area of the electronic components in that ENI by synthesizing all the blocks presented in [36] with a 40-nm industrial technology library, and obtained about 0.15 mm 2 .…”

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques

“…The design of interface is a challenging task due to the different signal frequencies between electrical and optical domains [13] [14]. For example, a modulation frequency F mod set to 10GHz provides a throughput of 10Gbit/s on 1-bit serial data transmission.…”

“…by using a Hamming decoder with a size similar to the coder. This paper does not investigate data flow control and multi-wavelenghts allocation, which have already been efficiently addressed in [13] and [14], respectively.…”

Proton+

“…We assume a core size and a die size of 1.33mm × 1.33mm and 9mm × 9mm respectively. Therefore cores occupy about 57mm 2 of the available 81mm 2 , the rest is being occupied by the on-chip electronic network (roughly 3.5mm 2 for the target system size), by I/O peripherals, by TSV arrays, and by the electronic circuits needed to drive the optical hubs [Ortín-Obón et al 2014]. Three different kinds of communication have to be enabled: a) between clusters, b) from a cluster to an off-chip memory connected to the optical layer, and c) from a memory to a cluster.…”