Proton+

Abstract

Optical Networks-on-Chip (ONoCs) are a promising technology to overcome the bottleneck of low bandwidth of electronic Networks-on-Chip. Recent research discusses power and performance benefits of ONoCs based on their system-level design, while layout effects are typically overlooked. As a consequence, laser power requirements are inaccurately computed from the logic scheme but do not consider the layout. In this article, we propose PROTON+, a fast tool for placement and routing of 3D ONoCs minimizing the total laser power. Using our tool, the required laser power of the system can be decreased by up to 94% compared to a state-of-the-art manually designed layout. In addition, with the help of our tool, we study the physical design space of ONoC topologies. For this purpose, topology synthesis methods (e.g., global connectivity and network partitioning) as well as different objective function weights are analyzed in order to minimize the maximum insertion loss and ultimately the system’s laser power consumption. For the first time, we study optimal positions of memory controllers. A comparison of our algorithm to a state-of-the-art placer for electronic circuits shows the need for a different set of tools custom-tailored for the particular requirements of optical interconnects.

ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip

“…We compare ToPro to three state-of-the-art physical design tools. In Section IV-A, we compare ToPro to the classical physical design tools, Proton+ [12] and PlanarONoC [13], for an 8-node processormemory network in terms of the worst-case insertion loss, the length of critical path, the number of crossings passed by the critical path, and program runtime. Furthermore, we tested ToPro on four different locations of memory-controllers proposed in [12] and compare our results with the results of Proton+ [12].…”

“…In Section IV-A, we compare ToPro to the classical physical design tools, Proton+ [12] and PlanarONoC [13], for an 8-node processormemory network in terms of the worst-case insertion loss, the length of critical path, the number of crossings passed by the critical path, and program runtime. Furthermore, we tested ToPro on four different locations of memory-controllers proposed in [12] and compare our results with the results of Proton+ [12]. In Section IV-B, we compare ToPro against PSION+ [15] for networks with 8 and 16 nodes in terms of the worst-case insertion loss, MRR usage, wavelength usage, and program runtime.…”

“…The Proton family of tools [11], [12] are the earliest physical design approaches for WRONoC. Given an input topology and the physical constraints, Proton+ uses a quadratic net model to synthesize the layout with adjustable optimization criteria concerning propagation loss and crossing loss.…”

“…The topological design focuses on the configuration of the MRRs, the wavelength assignment among different signal paths, and the interconnections between network components; and the physical design focuses on the placement of the network components and the routing of waveguides. To date, many efficient WRONoC topologies have been proposed, such as λ-router [7], Snake [8], GWOR [9], and Light [10], and several design automation tools have been developed to automate the physical design process, such as the Proton family of tools [11], [12], PlanarONoC [13] and the PSIONfamily of tools [14]- [16].…”

“…To prevent long detours of waveguides and extra waveguide crossings outside the OSEs, we propose to optimize the routing order of nets with an efficient method that systematically explores different ordering options. We compare ToPro to three state-of-theart physical design tools: Proton+ [12], PlanarONoC [13], and PSION+ [15]. The experimental results show that ToPro greatly accelerates the physical design process and shows superiority in energy-efficiency.…”