Problems and challenges of emerging technology networks−on−chip: A review

Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static-to-dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state-of-the-art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS-like, SDCVSL, and pseudo N-type, respectively, in terms of energy consumption.

show abstract

“…6 and 7, respectively. The equations under which PTI(AND) and PTI(NAND) return '0' ( 1and 2 PTI AND 0 Pull − Down = a 2 ⋅ b 2 (1)…”

Section: Primary Modelmentioning

confidence: 99%

“…The explosive growth of on-chip interconnections puts obstacles and bottlenecks in the way of optimising cost and performance of today's integrated circuits by posing signal integrity issues, routing complexities, crosstalk, and design challenges [1][2][3]. Multiplevalued logic (MVL) is a viable solution for this problem [4].…”

Section: Introductionmentioning

confidence: 99%

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Azimi

Mirzaee

Navi

et al. 2020

IET Computers & Digital Techniques

View full text Add to dashboard Cite

show abstract

“…Attackers try to undermine these three security aspects and SoC designers are required to obtain and keep the security goals to safeguard the system. While NoC security has been surveyed briefly in some previous works [16]- [19], to the best of our knowledge, there is no solid work that surveys the recent security solutions for various NoC technologies. This paper covers both the different attack models and the proposed countermeasures for wired, wireless, and 3D NoCs.…”

Section: Introduction E Ver Increasing Vlsi Technology Shrinkage Has Enabledmentioning

confidence: 99%

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

et al. 2021

View full text Add to dashboard Cite

Network-on-Chips (NoCs) have been widely used as a scalable communication solution in the design of multiprocessor system-on-chips (MPSoCs). NoCs manage communications between on-chip Intellectual Property (IP) cores and allow processing cores to achieve higher performance by outsourcing their communication tasks. NoC paradigm is based on the idea of resource sharing where hardware resources, including buffers, communication links, routers, etc., are shared between all IPs of the MPSoC. In fact, the data being routed by each NoC router might not be related to the router's local core. Such a utilization-centric design approach can raise security issues in MPSoCs-based designs, e.g., integrity and confidentiality of the data being routed in an NoC might be compromised by unauthorized accesses/modifications of intermediate routers. Many papers in the literature have discovered and addressed security holes of NoCs, aiming at improving the security of the NoC paradigm. However, to the best of our knowledge, there is no solid survey study on the security vulnerabilities and countermeasures for NoCs. This paper will review security threats and countermeasures proposed so far for wired NoCs, wireless NoCs, and 3D NoCs. The paper aims at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.

show abstract

“…Although conventional NoC‐based architectures have many remarkable advantages, some limitations including high latency, high power consumption and low bandwidth can appear due to the communication between long‐distance cores. To solve these problems, several new on‐chip communication solutions are investigated, such as radio frequency (RF)/micro‐wave interconnects technology, three‐dimensional (3D), and photonic NoCs [1]. Besides, based on the qualitative characteristics of the complementary metal‐oxide‐semiconductor (CMOS) wireless technologies, many researchers are focused on the integration of CMOS‐based wireless antennas on a chip.…”

Section: Introductionmentioning

confidence: 99%