Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Abstract

Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static-to-dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state-of-the-art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS-like, SDCVSL, and pseudo N-type, respectively, in terms of energy consumption.

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

“…In this case, the middle n‐type and p‐type transistors, which are constantly ON, perform voltage division, and both outputs become ‘1’. DCVSL circuits are usually fast, but many transistors are relatively consumed for the production of two outputs. The ternary dynamic DCVSL [139], Figure 4i, eliminates two networks from its static version. Pass transistor (PT) is a ubiquitous component for circuit design. In addition, a transmission gate (TG) is like a PT but ensures full‐swing signal transmission.…”

“… Well‐known logic styles for single‐V DD unbalanced ternary circuitry, (a) Ternary resistor transistor logic (RTL) [11], (b) Ternary pseudo‐NMOS logic [136], (c) Ternary CMOS logic style [12], (d) Ternary dynamic logic [137], (e) Ternary capacitive threshold logic (CTL) [65], (f) Negative ternary (NT)/Positive ternary (PT) functions [56], (g) Dynamic NT/PT functions [90], (h) Ternary DCVSL [138], (i) Ternary dynamic DCVSL [139], (j) MUX‐based approach [19], (k) Pass transistor (PT)/transmission gate (TG), (l) Decoder/Encoder [31], (m) Ternary current‐mode logic (CML) [66]. DCVSL, differential cascode voltage switch logic.…”

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

“…The ternary system (Low: 0 (0V), Middle: 1 (Vdd/2), and High: 2 (Vdd)), which is designed and implemented in this work, has a higher performance system among all known base systems [3]. Many researchers implement MVL in several applications like Machine learning and IoT [4], Algorithm [5], Data transmission [6], Healthcare [7], Combined with binary circuits [8], Resistive RAM or Memristor [9], [10], Ternary Converters [11], and ternary circuits [12], [13].…”