A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

Sarihi, Amin; Patooghy, Ahmad; Khalid, Ahmed; Hasanzadeh, Mahdi; Said, Mostafa; Badawy, Abdel-Hameed A.

doi:10.1109/access.2021.3100540

Cited by 22 publications

(10 citation statements)

References 122 publications

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“…[22] provides a extensive survey on network on chip attack and countermeasures which focus only on security of electrical NoCs. A recent survey [68] explores security on wired, wireless as well as 3-D NoCs. However, it has two major limitations.…”

Section: Major Differences With Existing Surveysmentioning

confidence: 99%

Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

Weerasena¹,

Mishra²

2023

Preprint

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The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital component in today's SoCs. Diverse technologies such as electrical, wireless, optical, and hybrid are available for on-chip communication with different architectures supporting them. Security of the on-chip communication is crucial because exploiting any vulnerability would be a goldmine for an attacker. In this survey, we provide a comprehensive review of threat models, attacks and countermeasures over diverse on-chip communication technologies as well as sophisticated architectures.CCS Concepts: • Hardware → Network on chip; • Security and privacy → Hardware security implementation.

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Section: Major Differences With Existing Surveysmentioning

confidence: 99%

Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

Weerasena¹,

Mishra²

2023

Preprint

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“…As an example, the HT in Figure 4 (in yellow) has the state vector s t = [2,1,3,4]. The action space of the described HT agent is multi-discrete, i.e., each input of the HT may choose an action from a set of five available actions.…”

Section: B Rl-based Ht Insertionmentioning

confidence: 99%

“…• Design source code or netlist can be infected with HTs by compromised employees. • Third-party intellectual properties (IPs) like processing cores, memory modules, I/O components, and networkon-chip [4] are often purchased and incorporated into a design to speed up time-to-market and lower design expenses. However, integrating IPs from untrusted vendors can pose a risk to the security and integrity of the IC.…”

Section: Introductionmentioning

confidence: 99%

Hardware Trojan Insertion Using Reinforcement Learning

Sarihi

Patooghy

Jamieson

et al. 2022

Proceedings of the Great Lakes Symposium on VLSI 2022

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Hardware Trojans (HTs) are undesired design or manufacturing modifications that can severely alter the security and functionality of digital integrated circuits. HTs can be inserted according to various design criteria, e.g., nets switching activity, observability, controllability, etc. However, to our knowledge, most HT detection methods are only based on a single criterion, i.e., nets switching activity. This paper proposes a multi-criteria reinforcement learning (RL) HT detection tool that features a tunable reward function for different HT detection scenarios. The tool allows for exploring existing detection strategies and can adapt new detection scenarios with minimal effort. We also propose a generic methodology for comparing HT detection methods fairly. Our preliminary results show an average of 84.2% successful HT detection in ISCAS-85 benchmarks.

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“…For establishing communication among these elements, traditional wiring becomes less reliable. The best available solution for these complex wiring issues in System on Chip (SoC) is network on chip (NoC) [1]- [3]. NoC has established itself as the most dependable and legitimate method of connecting multiple cores in a SoC.…”

Section: Introductionmentioning

confidence: 99%

Proficient matrix codes for error detection and correctionin 8-port network on chip routers

Neelima¹,

Kumar²,

Satyam³

et al. 2023

IJEECS

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This paper verifies the applicability of the proposed code to dynamic Network on Chips that have variable faulty blocks with runtime suggesting an online error detection mechanism with adaptive routing algorithm that bypasses faulty components dynamically and the router architecture uses additional diagonal state indications for the reliable network on chip (NoC) operation. In NoC, the permanently faulty routers are disconnected to enable high runtime throughput as data packets are not lost due to self-loopback mechanism. The proposed proficient matrix codes use the capabilities of decimal matrix code technique with minimum check bits for maximum error correction capability. The proposed code is compared with existing codes such as decimal matrix codes, modified decimal matrix codes and parity matrix codes. The codes are developed in verilog hardware description language and simulated in the Xilinx ISE 14.5 tool. This proficient matrix code proves to be efficient for multiple adjacent error detection and correction with trade off in delay. Also 65% code rate is achieved with 22.73% less redundant bits that occupy less area by atleast 11.78%. The codes when used for increased data sizes like 8, 16, 32, and 64 bits, the power delay product decreased by atleast 1.74%.

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A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

Cited by 22 publications

References 122 publications

Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

Hardware Trojan Insertion Using Reinforcement Learning

Proficient matrix codes for error detection and correctionin 8-port network on chip routers

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