Airgaps in nano-interconnects: Mechanics and impact on electromigration

Abstract

In this study, electromigration (EM) of interconnects (90 nm pitch) with airgaps was investigated using a combination of computational mechanics, analytical modelling, and EM experiments. EM experiments reveal that airgapped Cu lines without dielectric liner (non-capsulated) fail early by voiding in the EM tests due to oxidation and deterioration of interfacial adhesion at Cu interfaces. Also at high temperature regimes, extrusive failures under thermal compressive stresses were observed in airgapped Cu lines without dielectric liner. Therefore, Cu encapsulation using a conformal dielectric liner of adequate thickness is necessary in order to ensure hermeticity and provide endurance to the thermal and EM induced extrusive stresses. For an airgapped interconnect with a hermetic 5 nm PECVD conformal carbon doped silicon nitride (SiCN) liner deposited at 370 °C, a (jL)crit comparable to that of non-airgapped interconnects (with ultra-low-k dielectric 2.5 inter-layer dielectric) was predicted by the simulations. The process-oriented simulations reveal, however, that the tensile stress in Cu lines increases linearly with the thickness of the SiCN liner. Therefore, increasing the thickness of the dielectric liner beyond the minimum thickness required for hermeticity was found to impact the critical line length (jL)crit adversely.

Materials Quest for Advanced Interconnect Metallization in Integrated Circuits

“…[ 279 ] In addition, in contrast to the Cu AG method, which requires encapsulation of the hermetic dielectric layer to prevent oxidation, Ru has the advantage of limited surface oxidation. [ 280 ] Barrierless Ru combined with semi‐damascene allows for a smaller metal pitch. [ 62 , 278 , 281 ] Moreover, an adequate adhesion‐promoting layer to Ru‐dielectric interfaces provides mechanical integrity equivalent to the existing dual‐damascene Cu BEOL, even for a shape with an aspect ratio of 3.…”

Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

“…E a was derived using Black's equation by conducting EM experiments at different temperatures under constant current density. The values of Z, σ res and σ crit were obtained from [27]. The value of D 0 was then derived using the minimum Root Mean Square Error (RMSE) method, which minimizes the error between the modeled and measured TTFs at different temperatures.…”

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

“…160 The formation of air-gaps also introduces additional thermal-mechanical reliability concerns beyond those already typically associated with low-k dielectrics. [161][162][163][164] For these reasons, implementation of air-gap technologies in metal interconnects has been limited and only where there is substantial performance gain to be achieved.…”

“…2,3 Similarly, computational modeling had a profound impact on the development of low-k materials via providing insight into both structureproperty relationships [817][818][819][820] and process induced performance and reliability issues. [821][822][823] The optimal use of high-k and low-k dielectrics in both CMOS transistors, Cu interconnects, and pitchdivision patterning stacks was also guided by intensive computational device, 824 thermal-mechanical packaging reliability, 122,123,[162][163][164] and optical proximity correction (OPC) modeling. 147,243,825 Further, computational modeling has already played a significant role in guiding the selection of materials for future beyond CMOS devices and their optimization.…”