Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

Abstract

Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM analysis works focus on the power lines. There exists a limited amount of work which analyzes EM failures in the signal lines. However, various emerging spintronicbased memory technologies such as the Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) and the Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) have high current densities as compared to the conventional Static Random Access Memory (SRAM). These high current densities can lead to EM failures in the signal lines such as bit-line (BL) of these memories. Furthermore, these signal lines have workloaddependent stress as opposed to the conventional DC stress of power distribution networks. In this work, we model the EM failures in the BL of a typical STT memory array with realistic workloads. The analysis is based on physics-based EM model, which is calibrated based on industrial measurement data. The results show that the current densities in the STT arrays can be large enough to cause EM failures in the signal lines with running realistic workloads and that these failures are highly workload-dependent.

Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM

“…Method CAI: Current Averaging by Ignoring the idle cycles of the trace: This method has already been introduced in [8]. To calculate I seg with this method, we can use Eq.…”

“…Similar to [8], the STT-MRAM is organized in a 512 × 512 crossbar structure and the bit-line interconnect has a length of 200 nm for each cell, hence, the length of the bit-line will be 512 × 200 nm. The width and height of the bit-line are also 32 and 64 nm respectively.…”

“…According to [8], at the temperature of 100 • C and the aforementioned bit-line's dimensions, the values of σ res and σ crit are respectively 189.95 and 235.13 MPa. D 0 is assumed to be 7.7e − 10 m 2 s −1 and B is 13.4 Gpa.…”

“…Hence, most of the existing research work tried to capture the impact of the EM on the unidirectional power lines [4], [5]. However, due to the exacerbation of the EM risk in the more advanced technology nodes, some of the tight pitch signal lines especially in dense memory arrays, are also susceptible to the EM [6], [7], [8], therefore, EM modeling and studies are required for them.…”

“…By the aforementioned modeling and concepts, we are able to perform EM studies on the traces of realistic workload from SPEC CPU2017 benchmark suite. These traces are generated by reusing an extended version of the gem5 simulator that we have already used in [8].…”