FinFET transistors are commonly acknowledged as the most promising technology able to play a crucial role to route the development of rapidly growing modern silicon industry. Embedded memories, based on FinFET transistors, lead to new defect types that can require new embedded test and repair solutions. To investigate FinFET-specific faults, the existing fault models and detection techniques are not enough because of the spatial structure of FinFET transistors. This paper presents the results of the comprehensive study carried out for FinFET-based memories based on a new fault modeling and test algorithm creation strategy. The proposed solution is validated on several real FinFET-based embedded memory technologies.Index Terms-FinFET, defect, fault modeling, test algorithm, embedded memory.

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FinFET transistors are playing an i modern technology that is rapidly growing. Em based on FinFET transistors lead to new defects new embedded test and repair solution. To inv specific faults the existing models and detectio not enough due to a special structure of FinFET paper presents a new strategy for investiga specific faults. In addition to fault modeling, proposed for test algorithm synthesis. The propo is validated on several real FinFET-based em technologies. Moreover, new faults are identified only to FinFETs. Keywords-FinFET, defect, fault model, test alg memoryI.

This paper presents a robust solution for test and repair of embedded memories. The STAR (Self-Test and Repair) Memory System solution is developed within Synopsys DesignWare allowing users to create, integrate and verify embedded memory test and repair IP in system on chips. The key components and features of the SMS are discussed.