Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM

Nair, Sarath Mohanachandran; Bishnoi, Rajendra; Tahoori, Mehdi B.; Tshagharyan, G.; Grigoryan, H.; Harutyunyan, G.; Zorian, Y.

doi:10.1109/test.2018.8624725

Cited by 32 publications

(20 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Traditionally, a spot defect in an electronic circuit is modeled as a linear resistor, and the defect strength is represented by its resistance value [12,13,52]. For instance, missing material is modeled as a disconnection, while extra material is modeled as an undesired connection.…”

Section: Modeling Of Defects In Interconnects and Contactsmentioning

confidence: 99%

“…For instance, OB w denotes an open in the bit line disconnecting the memory cell with the write driver, while OB r denotes an open in the bit line disconnecting the memory cell with the sense amplifier. It is worth noting that some resistive defects are not realistic when considering the physical layout of the design, as also emphasized in [13]. For example, shorts connecting the inner node (between the MTJ and NMOS) to V DD or GND and bridges between the BL and WL are not possible, since they reside in different metal layers which are far away from each other [13].…”

Section: Modeling Of Defects In Interconnects and Contactsmentioning

confidence: 99%

“…Conventionally, MTJ-related defects irrespective of their physical natures are modeled as linear resistors either in series with (i.e., OC t in Table 4) or in parallel (i.e., S1 BL-IN in Table 5) to an idea defect-free MTJ device, as can be found in [8][9][10][11][12][13]. Comparing the fault modeling results of our proposed pinhole defect model (PH) with the series resistor model OC t and the parallel resistor model S1 BL-IN reveals the following.…”

Section: Pinhole Defects In Mtj Devicesmentioning

confidence: 99%

“…Chintaluri et al [11,12] have taken the fault modeling one step further by studying the impact of resistive defects while considering extreme process variations; they proposed a test algorithm and its built-in-self-test (BIST) implementation. Recently, Nair et al [13] have reported detailed STT-MRAM fault analyses, based on injecting resistors into layout-aware netlist. Nevertheless, prior work has three major limitations.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

View full text Add to dashboard Cite

STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

show abstract

Section: Modeling Of Defects In Interconnects and Contactsmentioning

confidence: 99%

Section: Modeling Of Defects In Interconnects and Contactsmentioning

confidence: 99%

Section: Pinhole Defects In Mtj Devicesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

View full text Add to dashboard Cite

show abstract

“…Table 3 summarizes the FFMs and how they contribute to read/write failures. Moreover, in [61], based on the defect injection scheme, defect characterization and fault modeling considering layouts for STT-MRAM are presented. In this analysis, a dynamic read fault behavior is demonstrated in which multiple vectors for excitation and detection are required.…”

Section: Mram Fault Modelsmentioning

confidence: 99%

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

View full text Add to dashboard Cite

| Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed Manuscript

show abstract

Memristor Based FPGAs: Understanding the Effect of Configuration Memory Faults

Schwarz

Hochberger²

2022

Architecture of Computing Systems

View full text Add to dashboard Cite

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM

Cited by 32 publications

References 24 publications

Defect and Fault Modeling Framework for STT-MRAM Testing

Defect and Fault Modeling Framework for STT-MRAM Testing

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

Memristor Based FPGAs: Understanding the Effect of Configuration Memory Faults

Contact Info

Product

Resources

About