Memory Physical Aware Multi-Level Fault Diagnosis Flow

Harutyunyan, G.; Martirosyan, Suren; Shoukourian, S.; Zorian, Y.

doi:10.1109/tetc.2018.2789818

Cited by 15 publications

(18 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Harutyunyan et al investigated the impact of resistive defects in FinFET-based memories and concluded that such memories are more susceptible to dynamic faults [27] than memories designed with planar technologies. Due to this distinction, they proposed a FinFET-specific March algorithm [12] that relies on the execution of up to 8 consecutive operations applied to the same cell. Faults that require more than 8 consecutive operations are not sensitized, and hence not detected.…”

Section: Finfet Testingmentioning

confidence: 99%

“…Weak resistive defects are known for causing dynamic faults, a subset of faults that are only sensitized by a sequence of consecutive operations. Many fault-oriented test approaches, such as standard March algorithms, do not target these types of faults [6][7][8] or are limited by the number of consecutive operations [9][10][11][12]. Using exhaustive March tests to sensitize faults results in expensive manufacturing tests, as the test cost is directly related to the time each product stays on the tester [13].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Medeiros

Poehls

Taouil

et al. 2018

Microelectronics Reliability

View full text Add to dashboard Cite

Resistive defects in FinFET SRAMs are an important challenge for manufacturing test in submicron technologies, as they may cause dynamic faults, which are hard to detect and therefore may increase the number of test escapes. This paper presents a defect-oriented test that uses On-Chip Current Sensors (OCCS) to detect weak resistive defects by monitoring the current consumption of FinFET SRAM cells. Using OCCS, all our single cell injected resistive defects have been detected within a certain accuracy by applying 5 read or write operations only, independent whether they cause static or dynamic faults. The proposed approach has been validated and the detection accuracy has been evaluated. Simulation results show that the approach is even able to detect weak resistive defects that do not even sensitize faults at the functional level, thus able to increase the reliability of devices.

show abstract

Section: Finfet Testingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Medeiros

Poehls

Taouil

et al. 2018

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…There are various memory test algorithms were introduced to test the memory devices [6,[10][11][12]. The conventional test algorithms are zero-one and checkboard scan tests.…”

Section: Introductionmentioning

confidence: 99%

“…New fault detection algorithms are proposed to detect memory faults, which are single-cell fault and two cells fault models. Some of the popular fault detection algorithms are Modified Algorithmic Test Sequence (MATS), MATS+, MATS++, Marching-1/0, March A, March B, March C, March C-, Extended March C-, March G, March X and March Y [10].…”

Section: Introductionmentioning

confidence: 99%

VHDL Modelling of Low-CostMemory Fault Detection Tester

Chun

Leong

Yoong

et al. 2020

JETAP

View full text Add to dashboard Cite

Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X ,March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100% fault detection coverage for all memory defects.

show abstract

“…Many test approaches to detect memory faults have been proposed in literature. Strong, deterministic faults can be detected by schemes that rely on logic faults observation, such as March algorithms [4][5][6][7][8]. Yet, many of these algorithms do not target or have limitations detecting hard-to-detect faults.…”

Section: Introductionmentioning

confidence: 99%

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Medeiros

Taouil

Fieback

et al. 2019

2019 IEEE European Test Symposium (ETS)

View full text Add to dashboard Cite

Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an important challenge for manufacturing testing in scaled technologies, as they may lead to test escapes. This paper proposes a Design-for-Testability (DFT) scheme able to detect such faults by monitoring the bitline swing of FinFET memories. Using only five operations per cell, we are able to detect defects that cause deterministic, random, and weak faults. Compared to the state of the art, this leads to an improved detection capability at reduced area overhead.

show abstract

Memory Physical Aware Multi-Level Fault Diagnosis Flow

Cited by 15 publications

References 13 publications

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

VHDL Modelling of Low-CostMemory Fault Detection Tester

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Contact Info

Product

Resources

About