Materials Quest for Advanced Interconnect Metallization in Integrated Circuits

Abstract

Integrated circuits (ICs) are challenged to deliver historically anticipated performance improvements while increasing the cost and complexity of the technology with each generation. Front‐end‐of‐line (FEOL) processes have provided various solutions to this predicament, whereas the back‐end‐of‐line (BEOL) processes have taken a step back. With continuous IC scaling, the speed of the entire chip has reached a point where its performance is determined by the performance of the interconnect that bridges billions of transistors and other devices. Consequently, the demand for advanced interconnect metallization rises again, and various aspects must be considered. This review explores the quest for new materials for successfully routing nanoscale interconnects. The challenges in the interconnect structures as physical dimensions shrink are first explored. Then, various problem‐solving options are considered based on the properties of materials. New materials are also introduced for barriers, such as 2D materials, self‐assembled molecular layers, high‐entropy alloys, and conductors, such as Co and Ru, intermetallic compounds, and MAX phases. The comprehensive discussion of each material includes state‐of‐the‐art studies ranging from the characteristics of materials by theoretical calculation to process applications to the current interconnect structures. This review intends to provide a materials‐based implementation strategy to bridge the gap between academia and industry.

Two-dimensional materials for future information technology: status and prospects

“…The potential applications of 2D materials in BEOL go beyond building devices to interconnect with siliconbased devices, and also have the potential to replace or enhance existing interconnect technologies [441,992,1034]. As technology nodes continue to advance and BEOL dimensions rapidly shrink, existing Cu interconnects face issues such as routing congestion and significant RC delays [1035]. To address these challenges, researchers [1034,1036] have proposed using conductive 2D materials like graphene as interconnect materials to reduce thin film resistance and signal delay, achieve higher integration density, and dissipate less heat.…”

Vacancy-Type Defects and Oxygen Incorporation in NiAl for Advanced Interconnects Probed by Monoenergetic Positron Beams and Atom Probe Tomography

“…According to the electrical resistivity models, including such phenomena, − the line resistivity is proportional to ρ 0 × λ for a given fixed line dimension, where λ is the mean free path for electron–phonon scattering. By using the so-called ρ 0 × λ products as a useful figure of merit, the search for alternative interconnect metals has been researched extensively. − Among several replacement candidates, Co and Ru have been mainly investigated. − The electrical resistivity model, however, does not involve variations in the surface scattering and grain boundary reflection due to their physical and chemical properties, such as interface roughness, grain structures, and impurity incorporations. Because they depend on deposition and postdeposition processes of the interconnects, detailed knowledge based on the characterization of metal interconnects and related materials is indispensable.…”

Investigation of Polisher Head and Slurry Sweep Effect in Oxide Film Polishing

“…The insulation layer between metal lines typically comprises dielectric materials, including TEOS, low-k material SiCOH, and materials containing nitrogen. 1 The CMP process involves two main steps: bulk material removal and buffing to achieve planarity. For effective bulk removal, a high RR is required to eliminate pattern features and to remove over-deposited materials.…”