A Survey and Taxonomy of GALS Design Styles

Teehan, Paul; Greenstreet, Mark R.; Lemieux, Guy

doi:10.1109/mdt.2007.151

Cited by 152 publications

(82 citation statements)

References 33 publications

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“…However, we have realized that in certain cases of coherent clocks that expression does not apply. Deep inside (1) lays the assumption that the probability distribution of data edges along the sampling clock period is uniform [2] [15]. However, we show that uniform distribution cannot be assumed in coherent clock domains.…”

Section: Introductionmentioning

confidence: 94%

“…Note that some cases of the loosely synchronous clocks may be either coherent or non-coherent, and hence it is impossible to unify the two different classifications. It is widely believed that loosely synchronous clock domains may be synchronized using either a special purpose synchronizer designed for each of the special cases(e.g., [7]- [11]), or using a brute-force ܰ-flip-flop synchronizer of the type designed for asynchronous domains [2] [3] [4] [19]. …”

Section: Introductionmentioning

confidence: 99%

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MTBF Estimation in Coherent Clock Domains

Beer

Ginosar

Dobkin

et al. 2013

2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems

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Abstract-Special synchronizers exist for special clock relations such as mesochronous, multi-synchronous and ratiochronous clocks, while variants of N-flip-flop synchronizers are employed when the communicating clocks are asynchronous. N-flip-flop synchronizers are also used in all special cases, at the cost of longer latency than when using specialized synchronizers. The reliability of N-flip-flop synchronizers is expressed by the standard MTBF formula. This paper describes cases of coherent clocks that suffer of a higher failure rate than predicted by the MTBF formula; that formula assumes uniform distribution of data edges across the sampling clock cycle, but coherent clocking leads to drastically different situations. Coherent clocks are defined as derived from a common source, and phase distributions are discussed. The effect of jitter is analyzed, and a new MTBF expression is developed. An optimal condition for maximizing MTBF and a circuit that can adaptively achieve that optimum are described. We show a case study of metastability failure in a real 40nm circuit and describe guidelines used to increase its MTBF based on the rules derived in the paper.

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Section: Introductionmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

MTBF Estimation in Coherent Clock Domains

Beer

Ginosar

Dobkin

et al. 2013

2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems

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“…Working environment of a synchronizer can be classified according to the frequency and phase difference, periodic nature of clocks, and the number of clock sources [3,4]. Table 1 summarizes the classification of working environments and methods of synchronization.…”

Section: Introductionmentioning

confidence: 99%

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Song¹,

Park²,

Lee³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

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“…It consists of synchronous module, stoppable clock, asynchronous wrapper, asynchronous router and on-chip buffer. Four-phase protocol is widely used in conventional NoC design [7][8][9] , because four-phase protocol can effectively reuse existing synchronous units, and it is suitable for designing function module in asynchronous router due to its design simplicity. But communications between asynchronous router and asynchronous wrapper always become the bottleneck when burst mode data transmission emerge.…”

Section: Introductionmentioning

confidence: 99%

Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips

Guan

Tong

Yang

2010

J. Comput. Sci. Technol.

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For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips, this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper. The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock. Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register, and then control the wrapper to sample input/output data. Sender wrapper and receiver wrapper consist of C elements and threshold gates, which ensure the quasi delay-insensitive characteristics and enhance the robustness. Simulations under different technology corners are implemented based on SMIC 0.18 µm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727 mW and 1.779 mW. Its advantages of high-throughput, low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.

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A Survey and Taxonomy of GALS Design Styles

Cited by 152 publications

References 33 publications

MTBF Estimation in Coherent Clock Domains

MTBF Estimation in Coherent Clock Domains

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips

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