In this paper, we propose a novel hardware architecture for an intra‐prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing 4×4 Hadamard transform and quantization during 16×16 prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix 0.35 µm TLM (triple layer metal) library.

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Abstract.A fast motion estimation algorithm based on the adaptive search range adjustment ͑ASRA͒ is presented. The size of search range for each block is adaptively controlled according to the initial cost at the search center, and then the full search algorithm ͑FSA͒ is performed to find the optimal matching block in the adjusted search range. The proposed method is implemented in H.264/AVC reference software ͑JM͒ to demonstrate its efficiency over the conventional FSA.

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