Hardware-Software Implementation of MPEG-4 Video Codec

Kim, Seong–Min; Park, Ju-Hyun; Park, Seongmo; Koo, Bontae; Shin, Kyoung-Seon; Suh, Ki-Bum; Kim, Ig-Kyun; Eum, Nak-Woong; Kim, Kyung-Soo

doi:10.4218/etrij.03.0102.0019

Cited by 18 publications

(11 citation statements)

References 11 publications

(14 reference statements)

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“…Figure 7 shows the communication architecture on the inside of the processor. The details of the original implementation of the processor are well presented in [22]. Among these modules, the ARM7 core controls the entire chip and Direct Memory Access Controller/SDRAM Controller (DMAC/SDRAMC) interfaces with external SDRAM.…”

Section: Performance Estimationmentioning

confidence: 99%

On-Chip Bus Serialization Method for Low-Power Communications

Lee¹

2010

ETRI J

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One of the critical issues in on‐chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low‐power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word‐to‐word and bit‐by‐bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG‐4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost‐effective when implemented as a hardware circuit since its algorithm is very simple.

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Section: Performance Estimationmentioning

confidence: 99%

On-Chip Bus Serialization Method for Low-Power Communications

Lee¹

2010

ETRI J

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“…An interesting performance analysis for MPEG-4 comparing video codec SoC implementing multilayer bus architectures versus SoC implementing on-chip networks can be seen in [35][36][37].…”

Section: Hand-held Codecsmentioning

confidence: 99%

Advances in video coding for hand-held device implementation in networked electronic media

Núñez

2006

J Real-Time Image Proc

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This survey addresses a number of challenges and research areas identified in real time image processing for state-of-the-art hand-held device implementation in networked electronic media. The challenges appear when having to develop and map processing algorithms not only on fading, noisy, and multi-path band limited transmission channels, but more specifically here on the limited resources available for decoding and scalable rendering on batterylimited hand-held mobile devices. Networked electronic media requires scalable video coding which in turn introduces additional degradation. These problems raise some complex issues discussed in the paper. A need to extend, modify and even create new algorithms and tools, targeting architectures, technology platforms, and design techniques as well as scalability, computational load and energy efficiency considerations has established itself as a key research area. A multidisciplinary approach is advocated.

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“…In order to deal with different design requirements on digital signal processing including image processing system; e.g., video codec as a paradigm application utilized in many real-time applications for which many hardware and software implementations are already presented in literature [4][5][6][7]. Although software implementations are easy to realize on general-purpose microprocessors, multiprocessors, microcontrollers, or digital signal processors, their sequentially executing structure is not well suited for fast processing of computational applications such as high resolution compression/video scaling of motion pictures, satellite communication modulator/demodulator, etc [8].…”

Section: Introductionmentioning

confidence: 99%

A Low Cost High Speed FPGA-Based Image Processing Framework

Mahmoodi

Sayedi

2016

IJMECS

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Abstract-In this paper, a high-speed and low-cost image processing framework based on MATLAB-FPGA interface is proposed that can be used in researches aiming at developing wide variety of not only image processing tasks but also many signal processing applications. In addition, this new framework could be exploited for several other tasks such as on-chip verification, using PC as an enormous external RAM for FPGA while preserving high speed data access, developing hardware-software co-designs, etc. The communication between FPGA and MATLAB is via 1Gbs Ethernet based on UDP/IP protocol which is very promising for high speed data transmission in point-topoint communications. UDP stack is efficiently designed in FPGA based on a fully pipelined architecture with minimum level of logic in order to reach high performance.. Dynamic data transmission between the UDP stack, memory and an arbitrary image processing module makes it possible to practically simulate, debug and implement most relevant applications. The hardware system is relatively low-cost and it consumes a negligible area of a Spartan-6 LXT45 Xilinx FPGA. Operating at 1 Gb/s, theoretically, the system is capable of processing 132 frames of 640*480 color images in a second. The effectiveness of the system is evaluated by means of both place and route simulation and practical implementation of a skin detection algorithm and a motion detector.

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Hardware-Software Implementation of MPEG-4 Video Codec

Cited by 18 publications

References 11 publications

On-Chip Bus Serialization Method for Low-Power Communications

On-Chip Bus Serialization Method for Low-Power Communications

Advances in video coding for hand-held device implementation in networked electronic media

A Low Cost High Speed FPGA-Based Image Processing Framework

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