A suspension of cortical tissue fragments prepared by collagenase digestion of renal cortex obtained from fed and chronically acidotic (NH4Cl) rats was separated into four bands on a Percoll density gradient. By microscopic examination, vital staining with trypan blue, and histologic staining technique (periodic acid-Schiff) the F4 band was shown to contain only (greater than 98%) proximal tubules, whereas the F1 band was significantly enriched (70%) with distal tubules contaminated by glomeruli and short segments of proximal tubules. Intra/extracellular ratios for PAH of 15 were measured in the F4 band and of 2 in F1 band. ATP was 1.4 and 2.8 mumol/g in the F4 and F1 bands, respectively, and was stable for at least 60 min. The proximal F4 band was shown to be gluconeogenic (L-glutamine or L-lactate 2.5 mM as substrate) and to adapt to metabolic acidosis. The distal F1 band was shown to be glycolytic (glucose 2.5 mM) with no changes with acid-base status. All fractions were shown to metabolize glutamine, but the metabolic fate of this amino acid was different in proximal and distal structures. A F4/F1 activity ratio for the proximal cytoplasmic phosphoenolpyruvate carboxykinase enzyme of 2.6 and 4.3 was observed in normal and acidotic rats, respectively. In contrast, a F4/F1 ratio of 0.13 and 0.22 was observed for the distal cytoplasmic hexokinase enzyme. This preparation, therefore, allows the metabolism of a homogeneous population of proximal tubular fragments to be studied and can be used to obtain information on enzyme location within the nephron.

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| Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design.In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.KEYWORDS | Analog intellectual property (IP); intellectual property (IP) cores; network-on-chip (NoC); platform-based design; programmable intellectual property (IP); system-onchip testing; system-on-chip verification; system-on-chip (SoC)