Directional and single-driver wires in FPGA interconnect

Lemieux, Guy; Lee, E.; Tom, Marvin; Yu, Anthony J.

doi:10.1109/fpt.2004.1393249

Cited by 185 publications

(153 citation statements)

References 9 publications

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“…As seen in Figure 5.8, twice as many wires per channel are required for directional routing to include the same number of drivers as their bidirectional counterparts. However, experimentation indicates that roughly the same number of tracks per channel is needed to achieve the same routability for dir-tri [128] and singledriver switch implementations [128,136]. As a result of this track count finding, the overall area required to implement a dir-tri routing architecture was found to be about 20% less than the corresponding bidirectional equivalent [128].…”

Section: Logic Block Logic Blockmentioning

confidence: 83%

“…In contrast, a directional wire segment [239] is driven in a single direction. As seen in Figure 5.8(b), this halves the required tri-state buffers per switch [128]. Figure 5.9 shows two distinct choices that exist for the implementation of directional wire segment switches in a routing driver block.…”

Section: Unidirectional Single-driver Routing Architecturesmentioning

confidence: 99%

“…However, experimentation indicates that roughly the same number of tracks per channel is needed to achieve the same routability for dir-tri [128] and singledriver switch implementations [128,136]. As a result of this track count finding, the overall area required to implement a dir-tri routing architecture was found to be about 20% less than the corresponding bidirectional equivalent [128]. However, the directionality of wire segments was found to negatively impact the flexibility and drive capability of pass transistor connections from logic block outputs to wire segments, causing a delay increase of 3% for the dir-tri case versus a corresponding bi-directional architecture [128].…”

Section: Logic Block Logic Blockmentioning

confidence: 99%

“…As shown in Figure 5.8(a), bidirectional wires are connected with bidirectional switches (e.g., two back-toback tri-state drivers). The use of bidirectional wire segments can leave many routing switches unused [128]. Once programmed, each switch will be enabled to only drive one wire segment leaving the remaining switch resources unused.…”

Section: Unidirectional Single-driver Routing Architecturesmentioning

confidence: 99%

“…Additionally, each wire segment may be driven by one or more logic block output pins via a pass transistor. In [128], this implementation is referred to as a directional tri-state (dir-tri) implementation. An alternate approach to implementing directional wires is shown in Figure 5.9(b).…”

Section: Unidirectional Single-driver Routing Architecturesmentioning

confidence: 99%

See 4 more Smart Citations

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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Section: Logic Block Logic Blockmentioning

confidence: 83%

Section: Unidirectional Single-driver Routing Architecturesmentioning

confidence: 99%

Section: Logic Block Logic Blockmentioning

confidence: 99%

Section: Unidirectional Single-driver Routing Architecturesmentioning

confidence: 99%

Section: Unidirectional Single-driver Routing Architecturesmentioning

confidence: 99%

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FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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show abstract

Low-Power Techniques for FPGAs

Mehta

DeHon²

2010

Low-Power Variation-Tolerant Design in Nanometer Silicon

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Diffusion-Based Placement Algorithm for Reducing High Interconnect Demand in Congested Regions of FPGAs

Ali

Parvez

2014

Lecture Notes in Computer Science

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Abstract. An FPGA has a finite routing capacity due to which a fair number of highly dense circuits fail to map on a slightly under-resourced architecture. The high-interconnect demand in the congested regions is not met by the available resources as a result of which the circuit becomes un-routable for that particular architecture. In this paper we present a new placement approach which is based on a natural process called Diffusion. Our placer attempts to minimize the routing congestion by evenly disseminating the interconnect demand across an FPGA chip. For the 20 MCNC benchmark circuits, our algorithm reduced the channel width for 6 circuits. The results showed on average 11% reduction in standard deviation of interconnect usage at an expense of an average 5% penalty on wire length. Maximum channel width gain of 17% was also observed.

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Directional and single-driver wires in FPGA interconnect

Abstract: Abstract

Cited by 185 publications

References 9 publications

FPGA Architecture: Survey and Challenges

FPGA Architecture: Survey and Challenges

Low-Power Techniques for FPGAs

Diffusion-Based Placement Algorithm for Reducing High Interconnect Demand in Congested Regions of FPGAs

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