A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs

Petrescu, V.; Pelgrom, Marcel; Veendrick, H. J. M.; Pavithran, Praveen V; Wieling, J.

doi:10.1109/isscc.2006.1696283

Cited by 20 publications

(6 citation statements)

References 2 publications

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“…Signals in data/address buses and in clock distribution are also susceptible to SI loss. Furthermore, an important criterion in the selection of interconnects is that built-in monitors for SI testing may also allow probing of the signals that are otherwise difficult to observe due to the large number of metal layers and high metal density [14]. This particularly occurs in nanometer CMOS ICs.…”

Section: Signal Integrity Qualitymentioning

confidence: 99%

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Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Champac

Avendano²,

Figueras

2010

IEEE Trans. VLSI Syst.

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Abstract-Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

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Section: Signal Integrity Qualitymentioning

confidence: 99%

“…However, all possible operational conditions are unlikely to be taken into account by the present state-of-the-art computer-aided design (CAD) tools. Consequently, chips fail although they passed standard test procedures [14].…”

mentioning

confidence: 99%

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Champac

Avendano²,

Figueras

2010

IEEE Trans. VLSI Syst.

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“…Such strong correlation confirms the suitability of ringos to evaluate product speed. Therefore system integrity self test (SIST) modules, containing ringos, are placed within products [9], and used in all advanced technology nodes.…”

Section: Proving Process Capabilitymentioning

confidence: 99%

Validating foundry technologies for extended mission profiles

Dijk

Volf

Detcheverry

et al. 2010

2010 IEEE International Reliability Physics Symposium

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“…Alternatively, a sufficiently stable supply/reference ( 10 mV change) can be created and the temperature variation can be handled by a lookup table approach. Temperature dependent calibration values are then stored in a table and by monitoring in what temperature range the chip functions [20] correct values can be loaded.…”

Section: Sensitivity To Environmental Parametersmentioning

confidence: 99%

A 150 MS/s 133$~\mu$W 7 bit ADC in 90 nm Digital CMOS

Plas

Verbruggen

2008

IEEE J. Solid-State Circuits

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In recent years the energy efficiency of A/D converters has been improved significantly. Only 5 years ago [3] an energy efficiency of 1 pJ/conversion step was considered state-of-the-art. Now power efficiencies are reported in fJ/conversion step. In this paper two new converter techniques are presented that further improve upon reported energy efficiencies of A/D converters. The first technique implements the quantization with a comparator-based asynchronous binary search (CABS). The second technique implements the SAR control algorithm on the comparators (SAR-CC) that are also used to do the quantization. Both these techniques have been applied in a fully dynamic 7 bit A/D converter that uses a two-step 1b coarse and 6b fine architecture [2]. The 1b coarse converter is implemented using the SAR-CC principle, the 6b fine converter is implemented using the CABS principle. The 7 bit prototype implementation in 90 nm digital CMOS on a 1 V supply achieves 6.4ENOB, 40 dB SNDR at 150 MS/s consuming 133 W giving 10 fJ/conversion step energy efficiency (FOM). A second prototype implementing a stand-alone 6b CABS converter (the sub-A/D converter of the 7 bit converter) achieves 32 dB SNDR at 250 MS/s with 140 W of power consumption, which results in a FOM of 15 fJ/conversion step.

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A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs

Cited by 20 publications

References 2 publications

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Validating foundry technologies for extended mission profiles

A 150 MS/s 133$~\mu$W 7 bit ADC in 90 nm Digital CMOS

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