A 150 MS/s 133$~\mu$W 7 bit ADC in 90 nm Digital CMOS

Abstract

In recent years the energy efficiency of A/D converters has been improved significantly. Only 5 years ago [3] an energy efficiency of 1 pJ/conversion step was considered state-of-the-art. Now power efficiencies are reported in fJ/conversion step. In this paper two new converter techniques are presented that further improve upon reported energy efficiencies of A/D converters. The first technique implements the quantization with a comparator-based asynchronous binary search (CABS). The second technique implements the SAR control algorithm on the comparators (SAR-CC) that are also used to do the quantization. Both these techniques have been applied in a fully dynamic 7 bit A/D converter that uses a two-step 1b coarse and 6b fine architecture [2]. The 1b coarse converter is implemented using the SAR-CC principle, the 6b fine converter is implemented using the CABS principle. The 7 bit prototype implementation in 90 nm digital CMOS on a 1 V supply achieves 6.4ENOB, 40 dB SNDR at 150 MS/s consuming 133 W giving 10 fJ/conversion step energy efficiency (FOM). A second prototype implementing a stand-alone 6b CABS converter (the sub-A/D converter of the 7 bit converter) achieves 32 dB SNDR at 250 MS/s with 140 W of power consumption, which results in a FOM of 15 fJ/conversion step.

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

“…Hence, the quantization time allocated to each bit is no longer limited by the slowest conversion bit, but rather is affected by the average conversion time, leading to speed enhancement in comparison to synchronous architectures. Asynchronous architectures have been used frequently in recent designs [26,27,57] to shorten the overall conversion time. While an asynchronous technique helps to achieve higher speeds, it usually requires more complicated digital blocks to generate signals with unequal pulse widths.…”

“…The comparator-based asynchronous binary search (CABS) ADC [26] can be regarded as an architecture in between the flash and SAR ADCs, having characteristics that resemble both types. Unlike a SAR ADC, which employs one comparator (for 1 bit/cycle) and varying reference levels for each cycle, a CABS ADC consists of a comparator tree.…”

Wide‐tuning range programmable threshold comparator using capacitive source‐voltage shifting

“…Third, for certain applications where there are only two clocking phases available [2, 3], the addition of the extra shift clocking phase can complicate implementation or add to the critical delay path. However, in many cases only the comparator's decision delay is a part of the critical timing path [4]. In these situations, the extra phase is not a major concern or penalty.…”

“…A common scheme for generating a programmable threshold is to place tunable capacitances or tunable current sources at the drain nodes of the input pair of the first stage of the comparator, and sense the difference in integrated voltage on these nodes with a latch [1, 2, 4]. For example, in Fig.…”

On-chip data communication : analysis, optimization and circuit design

“…Sense amplifiers (SA) are hence widely applied in e.g. logic, memories, I/O data receivers [158], A/D converters [159][160][161][162], and more recently also in on-chip transceivers [20,33,61,67,69,72,77,84,85,121,124].…”