Abstract-Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.
In this paper, an auto-calibrated PVT (process, voltage, temperature) monitoring system based on delay chains and flip-flops is presented. The system and method are proposed to be used by IP's (Intellectual property) that require to monitor PVT conditions during its operation and depending on the detected changes be configurable or adaptive. The methodology is based on embedded PVT monitors that sense when the propagation delay variation in standard cells reaches a certain threshold. The system implementation is intended to be done since the RTL (register transfer level) design stage to avoid or reduce the full custom design effort. The PVT monitors are built using buffers from a technology design kit. The information of the PVT monitors is sent to a logic module that calibrates the monitors to choose the best monitoring option depending on the PVT corner, available clock, and standard cells delay. The system includes also a logic module that collects and sends the data inside or outside the chip, in parallel or serial modes. Characterization results of the PVT monitors are presented including different delay chains, and clock combinations trough different PVT corners. This system is intended to detect the change of the propagation delay in the cells due to the PVT conditions combined, and not to provide the stand-alone value of voltage, temperature, or process. Otherwise, one of the reasons for this proposal is to avoid the use of individual sensors.
Clk
SDCCombinational logic D Q D Q SDC SDC Sequential circuit timing path To other controllable flip flops in the same domain SDC Control tpcq tsetup tpcq tpd Abstract-A Controllable flip flop design for sequential synchronous systems is proposed. The flip-flop setup time and propagation delay is controlled with an additional setup time and delay control (SDC) input. With this SDC enable, it is possible to enhance the circuit timing performance when required. In this paper, it is shown that when the SDC input is enabled, the flipflop setup time and Clk-Q propagation delay are reduced, and when the SDC control remains disabled, the flip-flop reduces its timing margin saving power. The proposed flip-flop is designed and characterized in a TSMC 28 nm bulk CMOS technology.
Interconnect structures in high speed circuits play an important role in present CMOS technologies. Inductance and capacitance coupling effects (crosstalk) may cause a significant loss in signal integrity in high performance systems. One way to reduce these effects is to place a signal line between two grounded lines (shield). In this paper we study the influence of defective grounding of shielding lines.
We focus on resistive open defects due to manufacturing problems or broken vias. Faulty shields may cause undershoots or ringings in signal traveling in long interconnect lines. Simple expressions for undershoots and overshoots have been derived using dominant poles and employed to determine the zones of signal integrity violation for different lengths of interconnect lines.The results show the impact of defective grounded shields.
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