Signal integrity verification using high speed monitors

Avendano, V.; Champac, Victor; Figueras, Joan

doi:10.1109/etsym.2004.1347622

Cited by 5 publications

(2 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This monitor is composed of a differential pair with a latch as load (see Fig. 4) [29]. The latch is built with two cross-coupled pMOS transistors.…”

Section: B Testing Noise Violationsmentioning

confidence: 99%

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Champac

Avendano²,

Figueras

2010

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

show abstract

“…This monitor is composed of a differential pair with a latch as load (see Fig. 4) [29]. The latch is built with two cross-coupled pMOS transistors.…”

Section: B Testing Noise Violationsmentioning

confidence: 99%

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Champac

Avendano²,

Figueras

2010

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…The fiber weave and resin have relatively dielectric constant (Dk) of~6 and~3, respectively, presenting a nonhomogeneous medium for signal transmission. The performance of differential transmission traces is dependent upon the underlying material properties of the laminates used [1][2][3][4][5][6][7]. At high edge rates, especially transmission rates exceeding 25 Gbps, the impact of the fiber weave effect on high-speed signal transmission becomes non-negligible.…”

Section: Introductionmentioning

confidence: 99%

Effect of Fiber Weave Structure in Printed Circuit Boards on Signal Transmission Characteristics

et al. 2019

View full text Add to dashboard Cite

In this paper, we characterized and compared signal transmission performances of traces with different specifications of fiber weave. Measurements demonstrated that the dielectric constant, impedance fluctuation, and differential skew were all affected by fiber weave style. For flattened fiber weaves, the dielectric constant fluctuation reached 0.18, the impedance fluctuation amplitude was 1.0 Ω, and the differential skew was 2 ps/inch. For conventional fiber weaves, the three parameters were 0.44, 2.5 Ω, and 4 ps/inch respectively. Flattened fiber weave was more favorable for high-speed signal control. We also discussed the other methods to improve the fiber weave effect. It turned out that NE-glass (new electronic glass) fiber weave also had better performance in reducing impedance fluctuation and differential skew. Furthermore, made the signal traces and fiber weave bundles with an angle or designing the long signal line parallel to the weft direction both are simple and effective methods to solve this problem.

show abstract

A critical-path monitor for DVFS systems without datapath replication

Aparicio

Ituero

López‐Vallejo

2014

Design of Circuits and Integrated Systems

View full text Add to dashboard Cite

The benefits of technology scaling have been accompanied by undesirable variations of a large number of parameters that need to be offset to ensure the proper operation of current electronic systems. Timing uncertainties are one of the most dangerous of these variation because they jeopardize the performance of the whole system. Critical-path monitors in conjunction with DVFS control systems have appear as a promising solution to these problems. Traditional approaches employ synthesized replicas of the critical-path to perform the measurement. This work proposes a novel method to measure the delay of a critical-path through a monitor that does not employ datapath replication, but rather takes the measurement from the actual critical path. The monitor has been validated in a 90 nm technology, it takes an area of 9623 µm 2 , consumes an energy per measurement of 38 pJ and achieves an accuracy of 30 ps for the worst technology corner.

show abstract

Signal integrity verification using high speed monitors

Cited by 5 publications

References 16 publications

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Effect of Fiber Weave Structure in Printed Circuit Boards on Signal Transmission Characteristics

A critical-path monitor for DVFS systems without datapath replication

Contact Info

Product

Resources

About