Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Abstract

Abstract-Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

Fast estimation of RL‐loaded microelectronic interconnections delay for the signal integrity prediction

“…The implementation of different functions in electronic boards necessitates complex structures interconnections. As reported in [2][3][4][5][6], the latter can be a source of signal degradations. For example, to ensure the synchronisation of the digital data [7], the signal integrity (SI) plays important roles.…”

Skew violation verification in digital interconnect signals based on signal addition

“…External at-speed testing may not be possible for the newest technologies, and verification of some internal nodes could de difficult. Hence, built-in methodologies are required to verify signal integrity violations more accurately [1,5,6]. Verification of the signal integrity using on-chip monitors appears as a good alternative for present and future nanometric integrated circuits.…”

Microelectronic interconnect modeling with a periodical lumped RLC-network

“…In fact, interconnection lines are susceptible to generating significant delays and losses, which can be a source of signal desynchronization at different stages of microelectronic systems, such as in clock tree networks [10][11][12]. To overcome this problem, deep investigations on signal integrity (SI) propagating in interconnection networks have been conducted [13][14][15][16][17][18].…”