A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface

Miura, Noriyuki; Koizumi, Yusuke; Take, Yasuhiro; Matsutani, Hiroki; Kuroda, Tadahiro; Amano, Hideharu; Sakamoto, R.; Namiki, Mitaro; Usami, Kimiyoshi; Kondo, Masaaki; Nakamura, Hiroshi

doi:10.1109/mm.2013.112

Cited by 30 publications

(19 citation statements)

References 6 publications

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“…Paired coils, one for the clock and the other for the data, are implemented as a channel. A high frequency clock (1 -8 GHz) is generated by a ring oscillator, and the serialized data are transferred in synchronization with the high frequency Figure 1: TCI with transmitter and receiver [8] clock directly through the driver. The driver and coil pair for sending data is called the Tx channel or TX, while the receiver and coil pair for receiving is called the Rx channel or RX.…”

Section: Inductive Coupling Channelsmentioning

confidence: 99%

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Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Nomura

Matsushita

Kadomoto

et al. 2018

IJNC

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A wireless inductive coupling ThruChip Interface (TCI) is a flexible system-in-package (SiP) technique which enables to build a powerful interconnection network between stacked chips. For easy use of TCI, we have developed intellectual properties (IPs), and proposed an interconnection network which can make the use of IPs. We also developed a real chip embedded the IP, and evaluated the performance. By stacking multiple chips with the proposed IP, an inter-chip network with link-to-link flow control by piggyback control is established. The new proposed escalator network which uses piggyback of the credit packets outperforms the ring network used in the first prototype by 28%-59% in terms of throughput. The performance overhead by the piggyback control was less than 3%-4% of that without control messages.

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Section: Inductive Coupling Channelsmentioning

confidence: 99%

“…We developed the first prototype of building block computational system called Cube-1 [8]. It consists of a low-power microprocessor called Geyser [9] and coarse grained accelerators called CMACube [10] connected with the wireless inductive coupling Thru-Chip Interface (TCI).…”

Section: Introductionmentioning

confidence: 99%

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Nomura

Matsushita

Kadomoto

et al. 2018

IJNC

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“…Cube-1 [9] is the first prototype of a heterogeneous multicore system using a host processor Geyser and multiple CMA accelerators. Cube-1 uses a 3-D SiP (System in Package) structure to connect multiple chips.…”

Section: Cube-1mentioning

confidence: 99%

“…Although the wireless inter-chip links support enough bandwidth (8Gbps) and DMA block data transfer mechanisms are provided in the router, it appeared that the data transfer time between Geyser and CMAs sometimes occupies more than 20% of total execution time [9].…”

Section: Cube-1mentioning

confidence: 99%

“…In Cube-1 [9], the first scalable heterogeneous multicore system using multiple CMAs, a MIPS R3000 compatible processor with fine-grained power gating Geyser [3] is used as a host processor. Although Cube-1 achieved a certain performance improvement with the use of multiple CMAs, the data transfer time between Geyser and CMAs sometimes limited the performance.…”

Section: Introductionmentioning

confidence: 99%

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A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

Mai

Ozaki

Koizumi

et al. 2015

IJNC

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Cool Mega Array (CMA) is an energy efficient reconfigurable accelerator consisting of a large PE array with combinatorial circuits and a small microcontroller. In order to enhance the energy efficiency of the total system, a co-processor design of CMA called CMA-Geyser is proposed. By partly replacing the programmable microcontroller by the host processor Geyser with a dedicated hardware controller, the setting up for the CMA and data transfer can be efficiently done.The design using 65nm CMOS process is compared with an off-loading style multicore system Cube-1. By eliminating the data memory required in Cube-1, CMA-Geyser reduced 21.3% of semiconductor area. Also, it achieved about 2.7 times performance of Cube-1 by the efficient data communication between host and the accelerator.

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