A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

Mai, Izawa; Ozaki, Nobuaki; Koizumi, Yusuke; Uno, R.; Amano, Hideharu

doi:10.15803/ijnc.5.1_239

Cited by 1 publication

(1 citation statement)

References 11 publications

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“…Many accelerators have improved the performance in some specific tasks [12]- [15]. Even some accelerators, which were implemented by such ALU grids as MuCCRA [16] and CMA [17], lack local memory along with each ALU. On the other hand, different realworld applications usually demand various specifications of local memory.…”

Section: Problems With Conventional and Modern Systolic Arraysmentioning

confidence: 99%

Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth

Iwamoto

Kikutani

Zhang

et al. 2020

IEICE Trans. Inf. & Syst.

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Jun IWAMOTO †a) , Yuma KIKUTANI †b) , Renyuan ZHANG †c) , Members, and Yasuhiko NAKASHIMA †d) , Fellow SUMMARY A paradigm shift toward edge computing infrastructures that prioritize small footprint and scalable/easy-to-estimate performance is increasing. In this paper, we propose the following to improve the footprint and the scalability of systolic arrays: (1) column multithreading for reducing the number of physical units and maintaining the performance even for back-to-back floating-point accumulations; (2) a cascaded peer-to-peer AXI bus for a scalable multichip structure and an intra-chip parallel local memory bus for low latency; (3) multilevel loop control in any unit for reducing the startup overhead and adaptive operation shifting for efficient reuse of local memories. We designed a systolic array with a single column × 64 row configuration with Verilog HDL, evaluated the frequency and the performance on an FPGA attached to a ZYNQ system as an AXI slave device, and evaluated the area with a TSMC 28nm library and memory generator and identified the following: (1) the execution speed of a matrix multiplication/a convolution operation/a light-field depth extraction, whose size larger than the capacity of the local memory, is 6.3× / 9.2× / 6.6× compared with a similar systolic array (EMAX); (2) the estimated speed with a 4-chip configuration is 19.6× / 16.0× / 8.5×; (3) the size of a single-chip is 8.4 mm 2 (0.31× of EMAX) and the basic performance per area is 2.4×.

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