Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth

Abstract

Jun IWAMOTO †a) , Yuma KIKUTANI †b) , Renyuan ZHANG †c) , Members, and Yasuhiko NAKASHIMA †d) , Fellow SUMMARY A paradigm shift toward edge computing infrastructures that prioritize small footprint and scalable/easy-to-estimate performance is increasing. In this paper, we propose the following to improve the footprint and the scalability of systolic arrays: (1) column multithreading for reducing the number of physical units and maintaining the performance even for back-to-back floating-point accumulations; (2) a cascaded peer-to-peer AXI bus for a scalable multichip structure and an intra-chip parallel local memory bus for low latency; (3) multilevel loop control in any unit for reducing the startup overhead and adaptive operation shifting for efficient reuse of local memories. We designed a systolic array with a single column × 64 row configuration with Verilog HDL, evaluated the frequency and the performance on an FPGA attached to a ZYNQ system as an AXI slave device, and evaluated the area with a TSMC 28nm library and memory generator and identified the following: (1) the execution speed of a matrix multiplication/a convolution operation/a light-field depth extraction, whose size larger than the capacity of the local memory, is 6.3× / 9.2× / 6.6× compared with a similar systolic array (EMAX); (2) the estimated speed with a 4-chip configuration is 19.6× / 16.0× / 8.5×; (3) the size of a single-chip is 8.4 mm 2 (0.31× of EMAX) and the basic performance per area is 2.4×.

A High-Performance Multimem SHA-256 Accelerator for Society 5.0

“…Despite these disadvantages, multicore CPUs and GPUs are currently considered to be the most applicable hardware platforms for calculating SHA-256 in Bitcoin mining and other blockchain networks. In another approach, the systolic array-based accelerator named EMAXVR in [13] and its improved version in [14] were applied to reduce the data access time by implementing local memory near the ALU. Although this platform achieves high performance on image processing and AI learning [13], [14], its performance for computing SHA-256 is very poor [15].…”

“…In another approach, the systolic array-based accelerator named EMAXVR in [13] and its improved version in [14] were applied to reduce the data access time by implementing local memory near the ALU. Although this platform achieves high performance on image processing and AI learning [13], [14], its performance for computing SHA-256 is very poor [15]. The key reason for the low processing rate is the data-dependent characteristic of the SHA-256 algorithm, as mentioned above.…”

MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security

“…We believe that with their high computational and memory resources, reprogrammable hardware design, low power consumption, and high optimization for parallel pipeline processes, FPGAs are well suited for Scrypt implementation. There are several high-performance architectures that can be applied on FPGAs to reduce the memory access time, such as the systolic-array-based accelerator called EMAXVR [41], [42] used in near-memory computing. However, despite exhibiting high performance in machine learning and image processing applications, they can achieve only poor performance when performing low-cost operator hash functions [43].…”

SLIT: An Energy-Efficient Reconfigurable Hardware Architecture for Deep Convolutional Neural Networks

“…FPGAs are suitable for computationally intensive algorithms that result in a faster speed and efficient energy. A few highlights of these approaches include parameter reduction, binary weight quantization, memory bandwidth optimization, and data-flow optimization [24]- [27]. A highly flexible architecture that can mold itself into the given CNNs and achieve a higher resource utilization reduction is essential.…”