A Novel Orthogonal Gate EDMOS Transistor With Improved  $dv/dt$ Capability and Figure of Merit (FOM)

Wang, Hao; Xu, H.P.E.; Ng, Wai Tung; Fukumoto, K.; Abe, Kanji; Ishikawa, Akira; Furukawa, Y.; Imai, H.; Naito, Takashi; Satô, Norio; Sakai, Kenichi; Tamura, Shigehiko; Takasuka, K.

doi:10.1109/led.2008.2007225

Cited by 10 publications

(6 citation statements)

References 3 publications

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“…LOCOS UMOS [13] 73 0.6 8.88 GE-UMOS [1] 141 The performance of the proposed structure is compared with those of the other MOSFET structures in Table 2. Except for the parameters of breakdown voltage (BV) and R ON , the figures of merit (FOMs) are also provided.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

Wang¹,

Jiao²,

Hu³

et al. 2012

Chinese Phys. B

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An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor (UMOSFET) integrated with a Schottky rectifier is proposed. In this device, a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET. Specific on-resistances of 7.7 mΩ·mm2 and 6.5 mΩ·mm2 for the gate bias voltages of 5 V and 10 V are achieved, respectively, and the breakdown voltage is 61 V. The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

Wang¹,

Jiao²,

Hu³

et al. 2012

Chinese Phys. B

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“…Via a trenched-gate, R ch could be greatly reduced. 11,12 The process for such topology relies on the STI technique or deep trench isolation (DTI), where a polysilicon electrode is deposited by CVD. 11 Again, this technique often requires an additional mask.…”

Section: Introductionmentioning

confidence: 99%

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

Houadef

Djezzar

2021

Int J RF Microw Comput Aided Eng

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In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (R ON,SP ) is 94 mΩmm 2 , and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (g m ) at high gate voltages, with acceptable off-state leakage current (I off ), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (f MAX ) and cutoff frequency (f T ) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers.

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“…The development of suitable power devices using CMOS is necessary to achieve its goal for system on chip (SOC) realization, [1][2][3][4][5][6][7][8][9][10][11] particularly in the low voltage range such as 30 V rating for RF wireless system, display driver, and DC-DC converter applications. [12][13][14][15][16][17][24][25][26][27][28] Laterally diffused metal oxide semiconductor (LDMOS) with double reduced surface field (RESURF) technology using low thickness of epitaxial layer or n-well implant has utilized for designing high-voltage devices with a low R on,sp . [18][19][20][21][22][23] Many studies show that high breakdown voltages can be maintained, while drift region doping concentration is increased by twice as much as that in single RESURF devices realizing a good trade-off between offstate BV and R on,sp .…”

Section: Introductionmentioning

confidence: 99%

A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage

Han

Chen

Chang

et al. 2012

Jpn. J. Appl. Phys.

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The multi-layer metals of Ni/AuGe/Pt/Au with a Pt diffusion barrier layer of ohmic contact to n-GaAs were studied. The surface morphology and ohmic contact resistivity of multi-layer metals were characterized, with and without the Pt diffusion barrier layer for comparison. The SEM and EDS measurements show the Pt diffusion barrier layer can block the interdiffusion of atoms in multi-layer metals, and improve the surface morphology. The TLM results show that the samples with a Pt diffusion barrier layer have uniform ohmic contact resistance, indicating that the Pt diffusion barrier layer can increase the repetition and uniformity of ohmic contact to n-GaAs, and improve the thermal stability and reliability of GaAs-based devices.

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A Novel Orthogonal Gate EDMOS Transistor With Improved $dv/dt$ Capability and Figure of Merit (FOM)

Cited by 10 publications

References 3 publications

A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage

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