A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

Wang, Ying; Jiao, Wen-Li; Hu, H.; Liu, Yuntao; Cao, Fei

doi:10.1088/1674-1056/21/5/056104

Cited by 2 publications

(1 citation statement)

References 13 publications

(11 reference statements)

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“…Tunneling field effect transistor (TFET) is based on the switching mechanism of band to band tunneling instead of thermionic emission as in the case of MOSFET. [1,2] Therefore, TFET does not suffer from the 60 mV/dec limit of the subthreshold swing (SS), rendering it promising for low-power applications.…”

Section: Introductionmentioning

confidence: 99%

Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures ^*

et al. 2017

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Tunneling field effect transistors (TFETs) based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low power devices. Here, we investigate the TFETs based on two different integration types: in-plane and vertical heterostructures composed of two kinds of layered phosphorous (β -P and δ -P) by ab initio quantum transport simulations. NDR effects have been observed in both in-plane and vertical heterostructures, and the effects become significant with the highest peak-to-valley ratio (PVR) when the intrinsic region length is near zero. Compared with the in-plane TFET based on β -P and δ -P, better performance with a higher on/off current ratio of ∼ 10 6 and a steeper subthreshold swing (SS) of ∼ 23 mV/dec is achieved in the vertical TFET. Such differences in the NDR effects, on/off current ratio and SS are attributed to the distinct interaction nature of the β -P and δ -P layers in the in-plane and vertical heterostructures.

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Section: Introductionmentioning

confidence: 99%

Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures ^*

et al. 2017

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Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-kdielectric trench

Wang¹,

Zhang²,

2013

J. Semicond.

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A novel silicon-on-insulator (SOI) MOSFET with a variable low-k dielectric trench (LDT MOSFET) is proposed and its performance and characteristics are investigated. The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region. At OFF state, the low-k dielectric trench (LDT) can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time, the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally, ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics, such as low gateto-drain charge density (< 0.6 nC/mm 2 / and a robust safe operating area (0-84 V).

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A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

Cited by 2 publications

References 13 publications

Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures ^*

Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures ^*

Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-kdielectric trench

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A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

Cited by 2 publications

References 13 publications

Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures *

Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures *

Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-kdielectric trench

Contact Info

Product

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About

Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures ^*

Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures ^*