A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage

Abstract

The multi-layer metals of Ni/AuGe/Pt/Au with a Pt diffusion barrier layer of ohmic contact to n-GaAs were studied. The surface morphology and ohmic contact resistivity of multi-layer metals were characterized, with and without the Pt diffusion barrier layer for comparison. The SEM and EDS measurements show the Pt diffusion barrier layer can block the interdiffusion of atoms in multi-layer metals, and improve the surface morphology. The TLM results show that the samples with a Pt diffusion barrier layer have uniform ohmic contact resistance, indicating that the Pt diffusion barrier layer can increase the repetition and uniformity of ohmic contact to n-GaAs, and improve the thermal stability and reliability of GaAs-based devices.

Low Specific On-resistance SOI LDMOS Device with P+P-top Layer in the Drift Region

“…Moreover, compared to the conventional D-RESURF device, the specific on-resistance of the P + P-top device decreases drastically. Actually, the optimal drift doping concentration in the conventional D-RESURF device can be calculated by [9]:…”

“…To address the issue, the Double RESURF (D-RESURF) concept has been introduced to improve this performance of the SOI LDMOS [8]. Many studies show that high breakdown voltage can be maintained, while drift region doping concentration is increased by about twice as much as that in S-RESURF devices, realizing a good trade-off between the breakdown voltage and specific on-resistance [9][10][11][12][13][14][15][16][17]. However, the surface electric field distribution of the D-RESURF device shows that a low valley value appears in the positive-biased P top N drift junction near the channel, thus leading to the breakdown voltage of the D-RESURF device is lower than that of the S-RESURF [9].…”

“…Many studies show that high breakdown voltage can be maintained, while drift region doping concentration is increased by about twice as much as that in S-RESURF devices, realizing a good trade-off between the breakdown voltage and specific on-resistance [9][10][11][12][13][14][15][16][17]. However, the surface electric field distribution of the D-RESURF device shows that a low valley value appears in the positive-biased P top N drift junction near the channel, thus leading to the breakdown voltage of the D-RESURF device is lower than that of the S-RESURF [9]. Furthermore, according to the RESURF principle, D-RESURF device is fairly strict with the charge control of the P-top layer, and the breakdown voltage is sensitive on the P-top layer doping concentration, length and depth, which increases the complexity of the device design and fabrication process invisibly [18].…”

Novel Bulk Silicon Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistors Using Step Thickness Technology in Drift Region

“…The reduced surface field (RESURF) technology is a common junction termination technology which is one of the most widely-used methods for the design of bulk silicon and silicon-on-insulator (SOI) power devices. 1) Various improvements on the basis of RESURF structure have been carried out, such as Double RESURF 2,3) and Triple RESURF, 4,5) can obtain a suitable trade-off between breakdown voltage (BV) and specific on-resistance (R on ). Although the RESURF devices are advantageous to reduce specific on-resistance, lateral electric field is still not effectively improved because the electric field is very low in the middle of the drift region.…”