The breakdown voltage (V BD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state V BD of 53.4 V is several times larger than V BD of 9.5 V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications. V

This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the Ion/Ioff current ratio is over 108 A/A for Lg = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust Vth in multi-Vth circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

The multi-layer metals of Ni/AuGe/Pt/Au with a Pt diffusion barrier layer of ohmic contact to n-GaAs were studied. The surface morphology and ohmic contact resistivity of multi-layer metals were characterized, with and without the Pt diffusion barrier layer for comparison. The SEM and EDS measurements show the Pt diffusion barrier layer can block the interdiffusion of atoms in multi-layer metals, and improve the surface morphology. The TLM results show that the samples with a Pt diffusion barrier layer have uniform ohmic contact resistance, indicating that the Pt diffusion barrier layer can increase the repetition and uniformity of ohmic contact to n-GaAs, and improve the thermal stability and reliability of GaAs-based devices.

The temperature-dependent performance, including drain current (I d) and gate capacitance (C gg) of multi-gate junctionless (JL) bulk transistor for temperature (T) ranging from 150 K to 500 K, was investigated using 3D thermodynamic quantum-corrected device simulation. The combination effect of impurity scattering and phonon scattering is observed owing to the different temperature-dependent of mobility at low and high temperature. Since the C gg of the JL device consists of a series combination of oxide capacitance (C ox) and semiconductor channel capacitance (C S) due to bulk conduction of the current, the C gg at on-state (V g ¼ 1 V) shows much sensitive to the temperature than a conventional inversion-mode transistor.