Temperature-dependent characteristics of junctionless bulk transistor

Han, Ming; Chen, Hung Bin; Yen, Shiang-Shiou; Shao, Chi-Shen; Chang, Chia-Chan

doi:10.1063/1.4821747

Cited by 12 publications

(5 citation statements)

References 14 publications

(32 reference statements)

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“…The ZTC of I-JL-NWFET and JL-NWFET are observed at 0.7 V and 0.8 V, respectively. In JL-NWFET, the primary degradation mechanism for electron mobility is phonon scattering, and this effect varies proportionally with T −3/2 [38]. However, the I D (V GS = 1 V) of I-JL-NWFET is comparatively high in comparison to JL-NWFET attributed to the incorporation of DMG that enhances the current driving capability in the device as observed in figure 17(a).…”

Section: Impact Of Temperature On Electrical Parametersmentioning

confidence: 99%

“…Figures 23(a) and (b) depict the C GG and f T as a function of V GS for temperatures ranging from 200 K to 500 K for I-JL-NWFET and JL-NWFET, respectively. From figure 23(a), it is perceived that, under low V GS , C GG is predominantly influenced by the depletion capacitance (C dep ) [38]. With the rising temperature, the surface potential diminishes, causing an enhancement in C dep .…”

Section: Impact Of Temperature On Analog/rf Parametersmentioning

confidence: 99%

“…As the temperature rises, I D initially rises at a specific V GS and subsequently declines with further temperature increases. This point is called the Zero Temperature Coefficient (ZTC) at which I D demonstrates almost no dependence on temperature [38]. Below the ZTC point, an increase in temperature leads to a decrease in V T , causing an increase in I D .…”

Section: Impact Of Temperature On Electrical Parametersmentioning

confidence: 99%

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Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Bharti,

Mittal

2024

Phys. Scr.

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An Improved Junctionless Nanowire Field Effect Transistor (I-JL-NWFET) device is proposed in this paper to address the limitations of conventional JL-NWFET. This research paper initially, comprehensively analyzes the impact of channel length (L) and channel thickness (t si ) scaling on the electrical, analog/RF, and linearity performance of I-JL-NWFET and JL-NWFET. The results suggest that the specific design features in I-JL-NWFET contribute to a more robust and less sensitive response to variations in scaling compared to its counterpart, JL-NWFET. Furthermore, an exploration into the impact of temperature on the electrical, analog/RF, and linearity performance is also conducted for both I-JL-NWFET and JL-NWFET. The electrical performance of I-JL-NWFET showcases a significantly reduced temperature sensitivity in parameters like drain current (I D ), Subthreshold Slope (SS) and Drain Induced Barrier Lowering (DIBL) compared to JL-NWFET. Subsequently, analyzing the analog/RF performance in the context of parameters such as transconductance (g m ), Transconductance Gain Factor (TGF), output conductance (g d ), early voltage (V EA ), total gate capacitance (C GG ), and cut-off frequency (f T ) under temperature variation, a lower degree of variability in I-JL-NWFET is observed compared to JL-NWFET. Furthermore, the linearity performance of I-JL-NWFET, assessed through parameters such as second and third-order transconductance (g m2 , g m3 ), second and third-order input voltage intercept points (VIP2, VIP3), and third-order intermodulation distortion (IIP3 and IMD3) is improved at the higher temperature than that of JL-NWFET.

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Section: Impact Of Temperature On Electrical Parametersmentioning

confidence: 99%

Section: Impact Of Temperature On Analog/rf Parametersmentioning

confidence: 99%

Section: Impact Of Temperature On Electrical Parametersmentioning

confidence: 99%

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Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Bharti,

Mittal

2024

Phys. Scr.

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“…This technology seems very different like a 'MOSFET without junctions', this statement can raise many questions regarding the physics of such devices. It is quite very important and desired to study the effects like non-uniform doping, the effect of temperature [82][83][84][85] (low, very low, high temperature), scattering effects, carrier mobility effects, misalignment of gates and many more. In this section, the above-said effects have been studied on various junctionless structures.…”

Section: Various Salient Effects On Operation and Characteristics Of ...mentioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

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The Short Channel Effects (SCE) are becoming more prominent in Complementary Metal Oxide Semiconductor (CMOS) circuits with an introduction of nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The short channel effects (SCE’s) and fabrication challenges have provoked the researchers to think for some other technologies to enhance the market of semiconductor devices. To overcome these SCE’s, various methodologies such as multi-gate structures, material engineering, gate engineering, dielectric pockets, strain technology, high K dielectric material, heterostructures, source and drain extensions etc. have been implemented. However, at very short channel lengths, the sharp edges of doping are difficult to obtain and thus SCE’s have become so difficult to control even after the implementations of different methodologies. Therefore, a new type of technology has been introduced to overcome such pitfalls e.g. transistors without junctions. Junctionless field effect transistor (JLFET) is one of the technologies which has overcome various SCE’s. Although the research on various issues has been addressed by different authors but still there is an impediment in the commercialization of the same device. The different technology boosters have been incorporated into junctionless based devices to escalate the performance. The technology boosting aspect of junctionless FET has been reviewed in this paper which has not been considered yet. In this paper distinct technology boosters and numerous effects on junctionless devices have been studied and presented. The performance of the junctionless FET devices are studied on incorporating the different semiconductor materials, effect of strain, use of high k dielectric, use of dielectric pockets, effect of gate misalignment, use of heterostructures, silicon on nothing (SON), vertically stacked nanowires, newly proposed rectangular core-shell based junctionless FET’s and roles of various physical parameters such as temperature, nanowire widths and effect of scattering mechanism on the performance of JLFET have been addressed.

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“…Figure 8(a) shows the I DS -V GS characteristics of the 1T-DRAM at temperatures of 300 and 358 K. The subthreshold characteristics in the 1T-DRAM degenerates with an increase in temperature because leakage currents are generated in the SRH, TAT, and BBT mechanism. 31,32) A high temperature induces a high generation=recombination rate. 33) Furthermore, I on decreases from 586.3 to 494.7 µA=µm owing to mobility degradation.…”

Section: T-dram Operation and Characteristicsmentioning

confidence: 99%

Capacitorless one-transistor dynamic random access memory based on double-gate GaAs junctionless transistor

Yoon

Seo

Cho

et al. 2017

Jpn. J. Appl. Phys.

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In this paper, we present a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a double-gate GaAs junctionless transistor (JLT). The proposed 1T-DRAM exhibits an excellent reading operation with a large sensing margin between the “1” and “0” states because the excess hole charges effectively screen the electric field formed by the gate2 voltage (VGS2). In order to reduce the electric field in the drain–gate interface involved in recombination, HfO2 is used as the spacer dielectric. The 1T-DRAM obtains a long retention time of 71 ms due to a low recombination rate. Moreover, we investigate the effect of geometric parameters on DRAM characteristics. The gate length (LG) and body thickness (Tbody) have a major impact on the sensing margin and retention time. The 1T-DRAM with a long LG and a thin Tbody can operate with a low power (LP) consumption, a long retention time, and high-density integration.

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Temperature-dependent characteristics of junctionless bulk transistor

Cited by 12 publications

References 14 publications

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Capacitorless one-transistor dynamic random access memory based on double-gate GaAs junctionless transistor

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