A NoC-based hybrid message-passing/shared-memory approach to CMP design

Casu, Mario R.; Roch, Massimo Ruo; Tota, Sergio V.; Zamboni, Maurizio

doi:10.1016/j.micpro.2010.09.006

Cited by 14 publications

(9 citation statements)

References 30 publications

(32 reference statements)

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“…Hybrid approaches, that efficiently support both shared-memory and message-passing programming paradigms, have recently been revived to fit systems on-chip [17,18]. The majority of NoC research focuses on mesh networks, due to their flexibility and regularity.…”

Section: Related Workmentioning

confidence: 99%

Hardware support for CSP on a Java chip multiprocessor

Gruian

Schoeberl

2013

Microprocessors and Microsystems

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a b s t r a c tDue to memory bandwidth limitations, chip multiprocessors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithreaded applications. Programmatically, the Communicating Sequential Processes (CSPs) paradigm provides a sound computational model for such an architecture with message based communication. In this paper we explore hardware support for CSP in the context of an embedded Java CMP. The hardware support for CSP are on-chip communication channels, implemented by a ring-based network-on-chip (NoC), to reduce the memory bandwidth pressure on the shared memory.The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. CMP architectures of three to eight processors were implemented and tested on both Altera (EP1C12, EP2C70) and Xilinx (XC3S1200e) FPGAs, showing that the NoC accounts for under 9% of the total device area used by the system. Compared to shared memory-based communication, our NoC-based solution is between 1.7 and 9.3 times faster for raw data transfer, depending on the communication and memory configuration. Application speed-up, on the other hand, is highly dependent on the type of processing, as our measurements show.

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Section: Related Workmentioning

confidence: 99%

Hardware support for CSP on a Java chip multiprocessor

Gruian

Schoeberl

2013

Microprocessors and Microsystems

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“…Using local memories in a NUMA architecture for messagepassing is a common approach [4,15], but generic all-to-all communication is potentially expensive in hardware. However, Section V shows that our low-bandwidth, write-only ring implementation can be kept low-cost.…”

Section: Related Workmentioning

confidence: 99%

An efficient asymmetric distributed lock for embedded multiprocessor systems

Rutgers

Bekooij

Smit

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-Efficient synchronization is a key concern in an embedded many-core system-on-chip (SoC). The use of atomic read-modify-write instructions combined with cache coherency as synchronization primitive is not always an option for sharedmemory SoCs due to the lack of suitable IP. Furthermore, there are doubts about the scalability of hardware cache coherency protocols. Existing distributed locks for NUMA multiprocessor systems do not rely on cache coherency and are more scalable, but exchange many messages per lock.This paper introduces an asymmetric distributed lock algorithm for shared-memory embedded multiprocessor systems without hardware cache coherency. Messages are exchanged via a low-cost inter-processor communication ring in combination with a small local memory per processor. Typically, a mutex is used over and over again by the same process, which is exploited by our algorithm. As a result, the number of messages exchanged per lock is significantly reduced. Experiments with our 32-core system show that when having locks in SDRAM, 35% of the memory traffic is lock related. In comparison, our solution eliminates all of this traffic and reduces the execution time by up to 89%.

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“…A major limitation in the use of SAs is that the pipeline level, required to reduce the critical path and to increase frequency, could limit the throughput in presence of feedback loops. By increasing the level of pipelining higher clock frequencies are allowed [14], but problems arise due to signal synchronization, in particular in presence of feedback signals. As a consequence, to synchronize signals the circuits operations must be slowed down, leading to a throughput that might be lower than the throughput obtained with a lower pipeline level and a lower clock frequency.…”

Section: Introductionmentioning

confidence: 99%

Interleaving in Systolic-Arrays: A Throughput Breakthrough

Causapruno

Vacca

Graziano

et al. 2015

IEEE Trans. Comput.

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In past years the most common way to improve computers performance was to increase the clock frequency. In recent years this approach suffered the limits of technology scaling, therefore computers architectures are shifting toward the direction of parallel computing to further improve circuits performance. Not only GPU based architectures are spreading in consideration, but also Systolic Arrays are particularly suited for certain classes of algorithms. An important point in favor of Systolic Arrays is that, due to the regularity of their circuit layout, they are appealing when applied to many emerging and very promising technologies, like Quantum-dot Cellular Automata and nanoarrays based on Silicon NanoWire or on Carbon nanotube Field Effect Transistors. In this work we present a systematic method to improve Systolic Arrays performance exploiting Pipelining and Input Data Interleaving. We tackle the problem from a theoretical point of view first, and then we apply it to both CMOS technology and emerging technologies. On CMOS we demonstrate that it is possible to vastly improve the overall throughput of the circuit. By applying this technique to emerging technologies we show that it is possible to overcome some of their limitations greatly improving the throughput, making a considerable step forward toward the post-CMOS era.Index Terms-Systolic arrays, CMOS, QCA, molecular QCA, nanoMagnet logic, NanoWire field effect transistor, interleaving Ç The authors are with the

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A NoC-based hybrid message-passing/shared-memory approach to CMP design

Cited by 14 publications

References 30 publications

Hardware support for CSP on a Java chip multiprocessor

Hardware support for CSP on a Java chip multiprocessor

An efficient asymmetric distributed lock for embedded multiprocessor systems

Interleaving in Systolic-Arrays: A Throughput Breakthrough

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