Interleaving in Systolic-Arrays: A Throughput Breakthrough

Abstract

In past years the most common way to improve computers performance was to increase the clock frequency. In recent years this approach suffered the limits of technology scaling, therefore computers architectures are shifting toward the direction of parallel computing to further improve circuits performance. Not only GPU based architectures are spreading in consideration, but also Systolic Arrays are particularly suited for certain classes of algorithms. An important point in favor of Systolic Arrays is that, due to the regularity of their circuit layout, they are appealing when applied to many emerging and very promising technologies, like Quantum-dot Cellular Automata and nanoarrays based on Silicon NanoWire or on Carbon nanotube Field Effect Transistors. In this work we present a systematic method to improve Systolic Arrays performance exploiting Pipelining and Input Data Interleaving. We tackle the problem from a theoretical point of view first, and then we apply it to both CMOS technology and emerging technologies. On CMOS we demonstrate that it is possible to vastly improve the overall throughput of the circuit. By applying this technique to emerging technologies we show that it is possible to overcome some of their limitations greatly improving the throughput, making a considerable step forward toward the post-CMOS era.Index Terms-Systolic arrays, CMOS, QCA, molecular QCA, nanoMagnet logic, NanoWire field effect transistor, interleaving Ç The authors are with the

Reconfigurable Systolic Array: From Architecture to Physical Design for NML

“…Moreover, in case of sequential circuits the intrinsic pipelining leads to a reduction of throughput of N times, where N is the length in clock cycles of the longest loop in the circuit [9]. This problem can be solved applying pipeline interleaving [11] [20], if several unrelated input sequences are available (Fig. 1…”

“…Actually a new operation cannot be started at every clock cycle, and the input data rate is reduced according to the length of the longest loop in the circuit [9] [10]. To solve this problem and exploiting the deep pipeline of the circuit at its best, pipeline interleaving can be introduced: It requires providing several unrelated input sequences, so as to fill the pipeline queue present in the loop and maximize the throughput [8] [11] (Fig. 1…”