An efficient asymmetric distributed lock for embedded multiprocessor systems

Rutgers, Jochem H.; Bekooij, Marco; Smit, Gerard J. M.

doi:10.1109/samos.2012.6404172

Cited by 4 publications

(2 citation statements)

References 19 publications

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“…RELATED WORK Researchers have acknowledged the importance of atomic operations in mutliprocessor system [11], as well as merge atomic memory operations with cache coherency [12]. Rutgers et al [13] proposes a distributed lock manager for embedded system without cache coherency, that is implemented on a FPGA. However, no work that uses our technique has been proposed in the past.…”

Section: Resultsmentioning

confidence: 99%

Managing mutex variables in a cache-coherent shared-memory system for FPGAs

Mirian

Chow

2012

2012 International Conference on Field-Programmable Technology

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Modern FPGAs have the ability to place many processing elements on a single die that can access shared memory. In a multiprocessing system, mutex variables are often used to provide proper synchronization and access to memory locations shared by the processing elements.This paper introduces a novel technique to manage mutex variables in caches for FPGAs, and is compared to an off-theshelf system built mostly by components from an FPGA vendor. Results show that a cache-coherent system using our proposed technique performs more barriers per second than the off-theshelf system with comparable hardware resources while also providing coherent caches.

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Section: Resultsmentioning

confidence: 99%

Managing mutex variables in a cache-coherent shared-memory system for FPGAs

Mirian

Chow

2012

2012 International Conference on Field-Programmable Technology

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“…For this, we use a 32-core MicroBlaze system [15,16], realized on FPGA using the Xilinx ML605 development board. It contains support to measure micro-architectural events, like ... tile n Figure 7.…”

Section: B Back-end Example: 32-core Microblaze Socmentioning

confidence: 99%

Portable Memory Consistency for Software Managed Distributed Memory in Many-Core SoC

Rutgers

Bekooij

Smit

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Abstract-Porting software to different platforms can require modifications of the application. One of the issues is that the targeted hardware supports another memory consistency model. As a consequence, the completion order of reads and writes in a multi-threaded application can change, which may result in improper synchronization. For example, a processor with out-of-order execution could break synchronization if proper fence instructions are missing. Such a bug can cause sporadic errors, which are hard to debug.This paper presents an approach that makes applications independent of the memory model of the hardware, hence they can be compiled to hardware with any memory architecture. The key is having a memory model that only guarantees the most fundamental orderings of reads and writes, and annotations to specify additional ordering constraints. As a result, tooling can transparently and properly implement fences, cache flushes, etc. when appropriate, without losing flexibility of the hardware design. In a case study, several SPLASH-2 applications are run on a 32-core software cache coherent MicroBlaze system in FPGA. Moreover, this approach also allows mapping to scratch-pad memories and a distributed shared memory architecture.

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