Real-time embedded systems like smartphones tend to comprise an ever increasing number of processing cores. For scalability and the need for guaranteed performance, the use of a connection-oriented network-on-chip (NoC) is advocated. Furthermore, a distributed shared memory architecture is preferred as it simplifies software development for a multicore system. In this paper, experimental evidence is provided, showing that replacing a connection-oriented NoC by a connectionless one in a distributed shared memory system reduces the hardware costs and improves the performance. We observed that our FPGA could only support an 8-core system with a connection-oriented NoC. We exchanged the NoC with our tree-shaped, connectionless network and a ring, allowing a 32core system in the same FPGA, mainly because of a reduced number of physical connections. Although the analytical worstcase performance slightly decreased, measurements show that the latency of latency-critical memory reads was reduced by 52% on average.
This paper presents the Darwin 1 project. This applied research project is currently conducted at Philips Medical Systems and focuses on the evolvability of software-intensive systems, with as use case Magnetic Resonance Imaging (MRI) systems. We not only discuss evolvability of software-intensive systems in general, but also describe the project and its research areas.
This paper presents the Darwin 1 project. This applied research project is currently conducted at Philips Medical Systems and focuses on the evolvability of software-intensive systems, with as use case Magnetic Resonance Imaging (MRI) systems. We not only discuss evolvability of software-intensive systems in general, but also describe the project and its research areas.Third IEEE Workshop on Software Evolvability 0-7695-3002-8/07 $25.00 The first research topic in this area concentrates on the communication in an MRI system: from the collection of the raw image data to the storage in a Picture Archiving and Communications System, from controlling the system to visualizing images, and from cables to communication protocols. The communication infrastructure of an MRI system impacts many system properties. For example, the amount of physical cables in an MRI system impacts the cost and ease-of-installation; the amount of connectors for the cables influences the reliability of the system; and the transport of data through the cables generates electric magnetic fields that negatively influence the image quality. A considerable part of the communication infrastructure of a Philips MRI system has been developed in-house. However, currently publicly-available and mass-marketed wired and wireless communication technologies might make it possible to replace proprietary solutions by general solutions and/or to reduce the number of physical cables by mapping multiple communication pathways onto a single cable. Models of the available hardware
Abstract-Porting software to different platforms can require modifications of the application. One of the issues is that the targeted hardware supports another memory consistency model. As a consequence, the completion order of reads and writes in a multi-threaded application can change, which may result in improper synchronization. For example, a processor with out-of-order execution could break synchronization if proper fence instructions are missing. Such a bug can cause sporadic errors, which are hard to debug.This paper presents an approach that makes applications independent of the memory model of the hardware, hence they can be compiled to hardware with any memory architecture. The key is having a memory model that only guarantees the most fundamental orderings of reads and writes, and annotations to specify additional ordering constraints. As a result, tooling can transparently and properly implement fences, cache flushes, etc. when appropriate, without losing flexibility of the hardware design. In a case study, several SPLASH-2 applications are run on a 32-core software cache coherent MicroBlaze system in FPGA. Moreover, this approach also allows mapping to scratch-pad memories and a distributed shared memory architecture.
Abstract-This paper presents an approximate Maximum Common Subgraph (MCS) algorithm, specifically for directed, cyclic graphs representing digital circuits. Because of the application domain, the graphs have nice properties: they are very sparse; have many different labels; and most vertices have only one predecessor. The algorithm iterates over all vertices once and uses heuristics to find the MCS. It is linear in computational complexity with respect to the size of the graph. Experiments show that very large common subgraphs were found in graphs of up to 200,000 vertices within a few minutes, when a quarter or less of the graphs differ. The variation in run-time and quality of the result is low.
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