In this paper, we present an algorithm for run-time allocation of hardware resources to software applications. We define the sub-problem of run-time spatial mapping and demonstrate our concept for streaming applications on heterogeneous MPSoCs. The underlying algorithm and the methods used therein are implemented and their use is demonstrated with an illustrative example.
Network -on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer's requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed. Cycle and bit accurate simulation is necessary when the actual router's RTL description needs to be evaluated and verified. However, extensive simulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming. In this paper we describe a simulation method to simulate large parallel homogeneous and heterogeneous network-on-chips on a single FPGA. The method is especially suitable for parallel systems where lengthy cycle and bit accurate simulations are required. As a case study, we use a NoC that was modelled and simulated in SystemC. We simulate the same NoC on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the Sys-temC simulation we achieved a speed-up of 80-300, without compromising the cycle and bit level accuracy.
Modern computers allow software to adjust power management settings like speed and sleep modes to decrease the power consumption, possibly at the price of a decreased performance. The impact of these techniques mainly depends on the schedule of the tasks. In this article, a survey on underlying theoretical results on power management, as well as offline scheduling algorithms that aim at minimizing the energy consumption under real-time constraints, is given.
Synchronous dataow (SDF) graphs are a widely used formalism for modelling, analysing and realising streaming applications, both on a single processor and a multiprocessing context. Ecient schedules are necessary to obtain maximal throughput with the optimum energy consumption in such a way that the number of resources used to run these applications is kept as low a possible. This paper presents an approach of scheduling SDF graphs using a proven formalism for timed systems called timed automata (TA). TA holds a good balance between the expressiveness and tractability, and are supported by many verication tools e.g. Kronos and Uppaal. We describe an algorithm for the compositional translation of SDF graphs to TA and implementation of the translation to analyse and verify SDF graphs in state-of-the-art tool Uppaal. This approach does not require any transformation of SDF graphs to HSDF graphs and helps to nd the schedules with a best compromise between number of the processors required and the throughput. It also allows quantitative model checking and verication of the user-dened properties like absence of deadlocks, safety, liveness and throughput analysis. The translation also forms the basis for future work of extending SDF graphs with the new features, e.g. stochastics, energy consumption and costs. This work also strives for bridging and extending the modelling computational formalisms towards energy aspects of self supporting computation. * This research has been supported by the EU FP7 project named SENSATION.
Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to implement, it is used in modern multicore processors like the IBM Power 7, ARM Cortex A9 and NVIDIA Tegra 2. This theory oriented paper discusses energy optimal DVFS algorithms for such processors.There are no known provably optimal algorithms that minimize the energy consumption of nontrivial real-time applications on a global DVFS system. Such algorithms only exist for single core systems, or for simpler application models. While many DVFS algorithms focus on tasks, this theoretical study is conceptually different and focuses on the amount of parallelism. We provide a transformation from a multicore problem to a single core problem, by using the amount of parallelism of an application. Then existing single core algorithms can be used to find the optimal solution. Furthermore, we extend an existing single core algorithm such that it takes static power into account.Keywords-Dynamic voltage and frequency scaling, energy minimization, mathematical programming, parallel processing I. INTRODUCTION As the power consumption of computing devices has increased exponentially [1], energy consumption has become one of the most important design criteria for these devices. For portable embedded devices this holds even more, since the energy-density of batteries does not grow with the same rate as the energy consumption of these devices.In this paper, we present algorithms for minimizing the energy consumption of a multicore system that executes a real-time application with precedence constraints. We focus on Dynamic Voltage and Frequency Scaling (DVFS) to decrease the energy consumption. DVFS allows for the decrease of the clock frequency and voltage of the processor, leading to a decrease of the power consumption, at the cost of an increased latency. Mathematical techniques and algorithms are frequently used to determine optimal clock frequencies. Such techniques are referred to as algorithmic power management [1], [2]. Based on a survey of such techniques by Irani and Pruhs [1], the current paper can be qualified as an algorithmic power management paper; we use algorithms to find clock frequencies that globally minimize the energy consumption.
In this paper, we define the problem of spatial mapping. We present reasons why performing spatial mappings at run-time is both necessary and desirable. We propose what is-to our knowledge-the first attempt at a formal description of spatial mappings for the embedded real-time streaming application domain. Thereby, we introduce criteria for a qualitative comparison of these spatial mappings. As an illustration of how our formalization relates to practice, we relate our own spatial mapping algorithm to the formal model.
Abstract-Design-time application mapping is limited to a predefined set of applications and a static platform. Resource management at run-time is required to handle future changes in the application set, and to provide some degree of fault tolerance, due to imperfect production processes and wear of materials. This paper concerns resource allocation at run-time, allowing multiple real-time applications to run simultaneously on a heterogeneous MPSoC. Low-complexity algorithms are required, in order to respond fast enough to unpredictable execution requests. We present a decomposition of this problem into four phases. The allocation of tasks to specific locations in the platform is the main contribution of this work. Experiments on a real platform show the feasibility of this approach, with execution times in tens of milliseconds for a single allocation attempt.
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