A Low Noise Wide Dynamic Range CMOS Image Sensor With Low-Noise Transistors and 17b Column-Parallel ADCs

Seo, Min-Woong; Sawamoto, Takehide; Akahori, Tomoyuki; Iida, Takuya; Takasawa, Taishi; Yasutomi, Keita; Kawahito, Shoji

doi:10.1109/jsen.2013.2264483

Cited by 25 publications

(18 citation statements)

References 23 publications

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“…A comparison of this work to another readout architecture for stacked imagers, also validated through a conventional CIS technology [9], and two works representing the state of the art in CIS technology with column parallel F-I/Cyclic ADC [23] and ISD ADC [16] is shown in Table I. Improvements of this work include the parallelism, the read noise and the frame rate.…”

Section: Resultsmentioning

confidence: 96%

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

2014

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The continuously increasing array resolution of CMOS imagers poses a great challenge in combining highframe-rate and low light detection in the same sensor. To cope with this, parallel readout architectures are needed. This paper proposes a readout architecture for 8K stacked image sensors, which uses a novel 1D decoding readout based on block-of-pixels and incremental-sigma-delta ADCs. The proposed 1D decoding system reduces the control lines of the pixels and allows a simpler decoding, an increased parallelism, and an improved robustness over process yield. The experimental results from a test chip implemented in a standard CIS technology show that at 10 μm pixel pitch, the proposed readout architecture can achieve a highframe-rate of 730 frames/s and a low read noise of 1.4 e − . In a real stacked implementation, the frame rate can further increase to about 960 frames/s at 8K resolution, at the cost of a slight increase in thermal noise by 14 μV.Index Terms-Image sensor, UHDTV, dynamic range, low noise, high frame rate, 3-D integration, stacked, high resolution, ADC, incremental .

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Section: Resultsmentioning

confidence: 96%

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

2014

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“…Two techniques are used for achieving the high pixel conversion gain. The first method helps to reduce the parasitic capacitance between the TG and FD node [7]. As placing a fully depleted diode structure between the TG and FD nodes, the coupling capacitance, which is generated between the TG and FD nodes, can be minimized.…”

Section: Pixel Design and Operationmentioning

confidence: 99%

“…To achieve high pixel conversion gain, the proposed pixel has two special in-pixel structures: 1) between the TG and FD node and 2) between the RG and FD node. The first method was already introduced in our previous work [7], and the second method is a new approach to eliminate the parasitic capacitance between the RG and FD node. The excellent noise level with very high, but relatively smaller conversion gain compared to [3], is attained by the FD node, which is less sensitive to noises from power lines, and the powerful 1/f noise reduction capability of readout circuitry [8].…”

Section: Introductionmentioning

confidence: 99%

A 0.27e-rms Read Noise 220-μV/e-Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11-μm CIS Process

Seo

Kawahito

Kagawa

et al. 2015

IEEE Electron Device Lett.

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A low temporal read noise and high conversion gain reset-gate-less CMOS image sensor (CIS) has been developed and demonstrated for the first time at photoelectron-counting-level imaging. To achieve a high pixel conversion gain without fine or special processes, the proposed pixel has two unique structures: 1) coupling capacitance between the transfer gate and floating diffusion (FD) and 2) coupling capacitance between the reset gate and FD, for removing parasitic capacitances around the FD node. As a result, a CIS with the proposed pixels is able to achieve a high pixel conversion gain of 220 µV/e − and a low read noise of 0.27e − rms using correlated multiple-sampling-based readout circuitry.Index Terms-CMOS image sensors (CISs), low read noise, high conversion gain, photon counting, photoelectron counting histogram (PCH).

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“…Several techniques have been proposed for a rail-to-rail (R2R) input. The most representative ones include -Native transistors (or natural transistors): They are a variety of the MOS field-effect transistor that is intermediate between enhancement and depletion modes, which have a nearly zero threshold voltage [2], [3]. The larger size due to additional doping mask, lower transconductance, and high cost due to additional doping operations are their main disadvantages.…”

Section: Introductionmentioning

confidence: 99%

Constant g<inf>m</inf> rail-to-rail CMOS OpAmp with only one differential pair and switched level shifters

Valero

Lopez-Martin

Roman‐Loera

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper introduces a simple approach for the implementation of rail-to-rail operational amplifiers (OpAmps) with constant g m using only one differential input pair. It is based on the utilization of switched voltage followers that introduce a DC level shift when the OpAmp's common mode input voltage is lower than the headroom of the input differential pair (DP). Additional circuitry is introduced in order to make the DP tail current insensitive to common mode input voltage variations. This improves CMRR and PSRR and reduces g m variations. The additional circuitry increases power dissipation by less than 20%. Simulation results are presented that verify rail-to-rail operation with ±1.65 supply voltages in 0.5µm CMOS technology.

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A Low Noise Wide Dynamic Range CMOS Image Sensor With Low-Noise Transistors and 17b Column-Parallel ADCs

Cited by 25 publications

References 23 publications

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

A 0.27e-rms Read Noise 220-μV/e-Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11-μm CIS Process

Constant g<inf>m</inf> rail-to-rail CMOS OpAmp with only one differential pair and switched level shifters

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