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In this paper, we describe the design and implementation of a one-chip camera device for a capsule endoscope. This experimental chip integrates peripheral circuits required for the capsule endoscope and the wireless transmission function based on a data transmission method using human body conduction. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). A prototype chip which has 320x240 effective pixels was fabricated using 0.25µm CMOS image sensor process and the autonomous imaging was demonstrated. The chip size is 4.84mmx4.34mm. With a 2.0 V power supply, the analog part consumes 950µW and the total power consumption at 6 fps (20MHz carrier frequency) is about 3mW.

Time-of-Flight (ToF) range imagers have a wide range of applications, such as 3D mice, gesture-based remote controllers, amusement, robots, security systems, and automobiles. Numerous ToF range imager developments have been reported [1][2][3][4]. Recent developments are often based on CMOS image sensor technology with pinned photodiode options [5][6][7], which are suitable for cost-effective mass production. Reported CMOS ToF range imagers use singletap or two-tap lock-in pixels; to cancel the influence of background light, two or four sub-frames are used to produce a background-canceled range image. These architectures, however, have difficulty with precise range measurements of moving objects, because background light cancelation is not guaranteed for moving objects. Lock-in pixels without any charge-draining gate suffer from background light during the readout time of the operation. Another important issue with CMOS ToF range imagers for high range resolution is the speed of lock-in pixels, which must be improved to use high-modulation-frequency light or short-duration light pulses.To address these problems and requirements, this paper presents a CMOS ToF range imager using pinned-photodiode high-speed lock-in pixels with background light-canceling capability. The lock-in pixel structure, which uses lateral electric field control, is suitable for implementing a multiple-tap charge modulator while achieving high-speed charge transfer for high time resolution. Figure 7.4.1 shows the charge modulator using lateral electric field control with three-tap outputs and a drain. In this lateral electric field modulator (LEFM), 4 sets of gates (G 1 , G 2 , G 3 and G D ) are used for applying a lateral electric field in the channel region created in a pinned diode. The gates are not used for transferring photo charge under the gates, but for controlling the electric field in the Y-Y` and X 1 -X 1` directions in Fig. 7.4.1. To do this, a small positive voltage (HIGH=1.8V) and negative voltage (Low=-0.8V) are used for the operation. As shown in the cross-section and potential profile of X 2 -X 2` in Fig. 7.4.1, the depleted potential of the pinned diode can be modulated by applying a negative or small positive voltage to the gates while maintaining the potential barrier to the gate region [8]. For example, when G 1 is HIGH and the others are LOW, the potential of the LEFM (see profiles of Y-Y` and X 1 -X 1`) attracts photo electrons generated in the aperture region to be transferred to a floating diffusion of the terminal T 1 . Similarly, photo electrons can be transferred to the terminal T 2 , terminal T 3 or the drain by applying a HIGH level to G 2 , G 3 , G D , respectively, and LOW levels to the others. During signal readout, a HIGH level is applied to G D , and LOW levels to the other gates for preventing the influence of background light. To realize a large potential modulation in the pinned diode, the doping concentration of the p-type epitaxial layer and surface p+ layer for hole pinning are optimized. Figure 7.4.2...