A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters

Kitamura, Keiichi; Watabe, Toshihisa; Sawamoto, Takehide; Kosugi, Tadayoshi; Akahori, Tomoyuki; Iida, Takuya; Isobe, Keigo; Watanabe, Takashi; Shimamoto, Hiroshi; Ohtake, Hiroshi; Aoyama, Satoshi; Kawahito, Shoji; Egami, Norifumi

doi:10.1109/ted.2012.2220364

Cited by 89 publications

(18 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Cyclic ADCs (which repeatedly use one unit of a pipelined ADC) and SAR ADCs have also been used in high-speed column ADCs. The 3.3 megapixel imager with the cyclic ADCs achieved 120 fps and 51.2 Gbps in 2012 [19]. The 1.42 megapixel imager with the SAR ADCs achieved 80 fps in 2013 [20].…”

Section: Column Adc Architecture For Image Sensorsmentioning

confidence: 99%

Recent progress in the technology linking sensors and digital circuits

Ikebe

2014

IEICE Electron. Express

View full text Add to dashboard Cite

Sensing systems perform digital-signal processing after converting analog input to digital output. These systems are used for various applications. This paper addresses the link between sensors and digital circuits. In particular, I address two areas: analog-todigital converter (ADC) architecture and signal processing for sensing systems, and then describe their demands. Each circuit and system processing method was investigated and their basic outlines are illustrated. Finally, recent trends in specific hardware implementations of these algorithms are discussed.

show abstract

Section: Column Adc Architecture For Image Sensorsmentioning

confidence: 99%

Recent progress in the technology linking sensors and digital circuits

Ikebe

2014

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Various architectures of column-parallel ADCs are investigated and implemented for CISs, such as single-slope ADC [1,2], successive approximation (SA) ADC [3,4], cyclic ADC [5,6], delta-sigma ADC [7,8], folding-integration/cyclic cascaded (FICC) ADC [9,10] and other hybrid ADCs [11,12]. As low noise, high resolution and high speed are required simultaneously for CISs in scientific, industrial and medical applications, the FICC ADC with multiple-sampling capability is a superior qualified candidate compared with other architectures of ADCs.…”

Section: Introductionmentioning

confidence: 99%

A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors

Wang

Seo

Yasutomi

et al. 2017

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

A high-resolution column-parallel folding-integration/cyclic cascaded (FICC) ADC with a pre-charging technique for CMOS image sensors is presented in this paper. To achieve high-resolution data conversion with multiple sampling, a pre-charging technique is applied to the sampling circuits of the FICC ADC to reduce the influence of incomplete discharging of historical previous samples. This technique effectively reduces differential nonlinearity of the ADC. The prototype chip with 1504 columns FICC ADC array has been implemented and fabricated in 110 nm CMOS technology. The measured DNL of column-parallel FICC ADC with 128 times multiple sampling is −1/4.73 LSBs in sampling speed of 13 KS/s and 19-bit resolution.

show abstract

“…This kind of architectures is not aligned to the trends of minimum size pixels and maximum spatial resolutions, pushed basically by consumer applications [26]. However, it is not clear that the quest for "as many pixels as possible" is pertinent for all applications.…”

Section: Introductionmentioning

confidence: 99%

A 151 dB High Dynamic Range CMOS Image Sensor Chip Architecture With Tone Mapping Compression Embedded In-Pixel

2015

View full text Add to dashboard Cite

This paper presents a high dynamic range CMOS image sensor that implements an in-pixel content-aware adaptive global tone mapping algorithm during image capture operation. The histogram of the previous frame of an auxiliary image, which contains time stamp information, is employed as an estimation of the probability of illuminations impinging pixels at the present frame. The compression function of illuminations, namely tone mapping curve, is calculated using this histogram. A QCIF resolution proof-of-concept prototype has been fabricated using a 0.35 µm opto-flavored standard technology. The sensor is capable of mapping scenes with a maximum intra-frame dynamic range of 151 dB (25 bits/pixel in linear representation) by compressing them to only 7 bits/pixel, while keeping visual quality in details and contrast. The in-pixel on-the-fly fully parallel tone mapping achieves high-frame rate allowing real-time high dynamic range video (120 dB at 30 frames/s).Index Terms-CMOS image sensor, high dynamic range, tone mapping, pulse width modulation, real-time HDR video.

show abstract

A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters

Cited by 89 publications

References 8 publications

Recent progress in the technology linking sensors and digital circuits

Recent progress in the technology linking sensors and digital circuits

A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors

A 151 dB High Dynamic Range CMOS Image Sensor Chip Architecture With Tone Mapping Compression Embedded In-Pixel

Contact Info

Product

Resources

About