This paper presents a novel column-parallel readout circuit for image sensors based on incremental-sigma-delta (ISD) ADCs. The excessive number of clock cycles needed per conversion is addressed. We apply the Photon Transfer Curve (PTC) based conversion to a second-order ISD ADC, achieving a 2.75x clock cycles reduction when compared to a standard secondorder ISD ADC while maintaining the same noise performance. This results in the reduction of the pixel readout time and of the size of the digital filter.
This paper presents a global-shutter imager readout architecture which allows a dynamic range of more than 132dB and a high frame rate. It is based on a stacked technology where the top tier contains the back-illuminated pixel array and the bottom one contains the sub-pixel logic array which implements the dynamic range extension by selecting the best integration time for each pixel. Experimental results of a 64 x 64 sub-pixel array confirm the effectiveness of the proposed method in extending the dynamic range by more than 10 bits. The application of the algorithm to higher array resolutions compromises its effectiveness given the increased column capacitance. As a way out, we propose a novel source-follower-based buffer which reduces the settling time of the sub-pixel without increasing its size. The performed analysis shows that the sensor can reach 1900fps and 375fps respectively at full HD and at 8K resolutions.
Abstract-This paper introduces a 3D-integrated image sensor with high dynamic range, high frame rate and high resolution capabilities. A robust algorithm for dynamic range extension with low sensitivity to circuit non-idealities and based on multiple exposures is presented. The impact of the TSV diameter over the dynamic range and frame rate performance is studied allowing the choice of the best 3D technology for the required performance.Keywords-component; 3D integration, CMOS image sensor, high frame rate, high dynamic range
The continuously increasing array resolution of CMOS imagers poses a great challenge in combining highframe-rate and low light detection in the same sensor. To cope with this, parallel readout architectures are needed. This paper proposes a readout architecture for 8K stacked image sensors, which uses a novel 1D decoding readout based on block-of-pixels and incremental-sigma-delta ADCs. The proposed 1D decoding system reduces the control lines of the pixels and allows a simpler decoding, an increased parallelism, and an improved robustness over process yield. The experimental results from a test chip implemented in a standard CIS technology show that at 10 μm pixel pitch, the proposed readout architecture can achieve a highframe-rate of 730 frames/s and a low read noise of 1.4 e − . In a real stacked implementation, the frame rate can further increase to about 960 frames/s at 8K resolution, at the cost of a slight increase in thermal noise by 14 μV.Index Terms-Image sensor, UHDTV, dynamic range, low noise, high frame rate, 3-D integration, stacked, high resolution, ADC, incremental .
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