A two-stage (Miller) operational amplifier (opamp) with both class AB input and output stages is introduced. It has a well-controlled quiescent current and generates dynamic output currents of up to a factor 45 times larger than the quiescent current. It uses very compact circuitry with small static power consumption in order to achieve class AB-AB operation and can operate with a low supply voltage. Experimental results of a test chip fabricated using 0.18 μm CMOS technology and simulations in 130, 90, 65 and 45 nm verify the proposed circuit.Introduction: The slew rate of a class A (two-stage) Miller operational amplifier (opamp) (Fig. 1a) is limited by the current in the input and output stages. A typical design with a high phase margin at unity gain has output transistors (M oP and M oN ) scaled by a factor 2 with respect to the transistors in the first stage (M 1 , M 1P , M 2 , M 2P ) a gain-bandwidth product GB and a compensation capacitor with value C C = C L . The maximum output current of the first stage is limited by the tail current to a value of 2I B . The maximum negative output current of the output stage (for opamps with an N-type metal-oxide-semiconductor (NMOS) input stage) has also a value of 2I B whereas the positive output current can have values much larger than 2I B . During slewing the output stage delivers current to both the load capacitor and the compensation capacitor whereas the input stage delivers current to the compensation capacitor C C . The internal positive and negative slew rates are symmetrical and given by SR int = 2I B /C C and the output node negative slew rate by SR out − = 2I B / (C C + C L ) = I B /C L whereas the positive output slew rate can be much larger since the current delivered by M oP during slewing is not limited by the bias current I B . It can be seen that in a typical design the negative output stage current limits the slew rate of the opamp. Class AB opamps with push-pull output stages are used to increase the slew rate. These opamps can deliver large positive and negative output currents I outP,N ≫ 2I B and are implemented by circuitry that performs as a floating battery connected between the high swing gate of M oP and the gate of M oN (Fig. 1b). Many implementations of the floating battery have been reported in the literature [1, 2]. One example of these architectures is the free class AB opamp (Fig. 1c) [3] that uses a capacitor connected between the gates of the output transistors and a moderately large resistor (∼100 kΩ) connected between the gate of the NMOS transistor and the bias voltage V bn that sets the quiescent current in M oN . Under dynamic conditions the capacitor keeps an approximately constant voltage between the gates of M oP and M oN and performs as a floating battery. Comprehensive surveys of class AB opamps are presented in [1,2]. The main requirement is that the value of V bat sets the quiescent current in M oN with a value equal to the quiescent current in M oP independent of the supply value; this avoids increased DC offsets and al...

Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and reduced settling time. The proposed compensation uses an auxiliary feedback to increase the total effective compensation capacitance without loading the output node. The proposed compensation scheme is validated in simulation by implementing a three-stage amplifier driving 10 pF load capacitor in a 0.18 μm CMOS process. A detailed comparison of the compensation with a conventional nested Miller compensation is also presented. The simulation results showed a reduction in total compensation capacitance and improvement in slew rate compared to conventional nested Miller compensation and the other reported techniques in the literature.

An efficient class-AB OTA with enhanced output current, slew rate, open loop gain, and gain bandwidth is presented. The circuit is based on a class-AB input stage with adaptive biasing, and an output stage with dynamically biased cascode transistors. It can deliver output currents 100 times larger than the bias current with a total quiescent power dissipation of 72 µW. Measurement results of a 180 nm CMOS test chip prototype show slew rate, gain bandwidth, and open loop gain enhancement.

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