A 0.27e-rms Read Noise 220-μV/e-Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11-μm CIS Process

Seo, Min-Woong; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita

doi:10.1109/led.2015.2496359

Cited by 79 publications

(19 citation statements)

References 11 publications

(14 reference statements)

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“…According to the typical conversion gain of 67 µV/e-for the case of a low-noise wide dynamic range image sensor [9], the error due to the ADC nonlinearity is less than 0.066e-. If the pixel has higher conversion gain like in [15], that is 220 µV/e-, the corresponding error due to the ADC nonlinearity can be less than 0.02e-. The maximum INL of 1,200 LSBs corresponds to 0.57% of the 38.6% of 19-bit full scale code (¼ 211;600).…”

Section: Simulation and Measurement Resultsmentioning

confidence: 99%

A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors

Wang

Seo

Yasutomi

et al. 2017

IEICE Electron. Express

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A high-resolution column-parallel folding-integration/cyclic cascaded (FICC) ADC with a pre-charging technique for CMOS image sensors is presented in this paper. To achieve high-resolution data conversion with multiple sampling, a pre-charging technique is applied to the sampling circuits of the FICC ADC to reduce the influence of incomplete discharging of historical previous samples. This technique effectively reduces differential nonlinearity of the ADC. The prototype chip with 1504 columns FICC ADC array has been implemented and fabricated in 110 nm CMOS technology. The measured DNL of column-parallel FICC ADC with 128 times multiple sampling is −1/4.73 LSBs in sampling speed of 13 KS/s and 19-bit resolution.

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Section: Simulation and Measurement Resultsmentioning

confidence: 99%

A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors

Wang

Seo

Yasutomi

et al. 2017

IEICE Electron. Express

Self Cite

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“…Studies have shown [5] that for a practical single-photon imager with negligible error rate the ENC must be below 0.15 e-RMS. Recent advances in CMOS image sensor (CIS) technology have reduced the readout noise significantly, and CIS with ENC below 0.3 e-RMS have been reported [6]- [8]. These developments are due to the increase of the conversion gain of the sensors above 200 µV/e-by the use of special design and processing techniques, as well as by improvements to the noise performance of MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Simulations and Design of a Single-Photon CMOS Imaging Pixel Using Multiple Non-Destructive Signal Sampling

Stefanov

Prest

Downing

et al. 2020

Sensors

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A single-photon CMOS image sensor design based on pinned photodiode (PPD) with multiple charge transfers and sampling is described. In the proposed pixel architecture, the photogenerated signal is sampled non-destructively multiple times and the results are averaged. Each signal measurement is statistically independent and by averaging the electronic readout noise is reduced to a level where single photons can be distinguished reliably. A pixel design using this method has been simulated in TCAD and several layouts have been generated for a 180 nm CMOS image sensor process. Using simulations, the noise performance of the pixel has been determined as a function of the number of samples, sense node capacitance, sampling rate, and transistor characteristics. The strengths and the limitations of the proposed design are discussed in detail, including the trade-off between noise performance and readout rate and the impact of charge transfer inefficiency. The projected performance of our first prototype device indicates that singlephoton imaging is within reach and could enable ground-breaking performance in many scientific and industrial imaging applications.

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“…The QLog pixel will exhibit a composed linear–logarithmic photo-electric response. The paper published at IISW2017 [7] indicates that this QLog pixel can be an elegant solution to overcome the too-low integration well capacity in actual high-sensitivity, subelectron readout noise sensors [8,9,10,11,12]. …”

Section: Introductionmentioning

confidence: 99%

QLog Solar-Cell Mode Photodiode Logarithmic CMOS Pixel Using Charge Compression and Readout

Ni¹

2018

Sensors

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In this paper, we present a new logarithmic pixel design currently under development at New Imaging Technologies SA (NIT). This new logarithmic pixel design uses charge domain logarithmic signal compression and charge-transfer-based signal readout. This structure gives a linear response in low light conditions and logarithmic response in high light conditions. The charge transfer readout efficiently suppresses the reset (KTC) noise by using true correlated double sampling (CDS) in low light conditions. In high light conditions, thanks to charge domain logarithmic compression, it has been demonstrated that 3000 electrons should be enough to cover a 120 dB dynamic range with a mobile phone camera-like signal-to-noise ratio (SNR) over the whole dynamic range. This low electron count permits the use of ultra-small floating diffusion capacitance (sub-fF) without charge overflow. The resulting large conversion gain permits a single photon detection capability with a wide dynamic range without a complex sensor/system design. A first prototype sensor with 320 × 240 pixels has been implemented to validate this charge domain logarithmic pixel concept and modeling. The first experimental results validate the logarithmic charge compression theory and the low readout noise due to the charge-transfer-based readout.

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A 0.27e-rms Read Noise 220-μV/e-Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11-μm CIS Process

Cited by 79 publications

References 11 publications

A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors

A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors

Simulations and Design of a Single-Photon CMOS Imaging Pixel Using Multiple Non-Destructive Signal Sampling

QLog Solar-Cell Mode Photodiode Logarithmic CMOS Pixel Using Charge Compression and Readout

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