A histogram based AM-BIST algorithm for ADC characterization using imprecise stimulus

Parthasarathy, K.L.; Jin, Le; Kuyel, T.; Chen, Degang; Geiger, R.L.

doi:10.1109/mwscas.2002.1186851

Cited by 11 publications

(6 citation statements)

References 5 publications

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“…An alternative is to measure transition times and calculate the values of transition levels by using (6). Substituting (15) into (6) (18) where is a scaling factor that scales the time period measured in terms of the number of samples to the normalized time defined earlier. Since the output code changes from 2 to 1 when , the total number of samples taken between and is given by…”

Section: B Linearity Testing For Adcsmentioning

confidence: 99%

“…Furthermore, such nonlinear sources can be placed on the device interface board (DIB) to reduce requirements and cost of the ATE or even incorporated on chip with a small die area to facilitate use in a design for test (DFT) or a built-in self-test (BIST) environment. Recent research using the concept of using nonlinear excitations for ADC testing can be found in [8], [9], [11]- [13], and [15]- [17]. As a proof of concept, two different approaches were discussed in the authors' previous work [8].…”

Section: Introductionmentioning

confidence: 99%

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Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal

Jin

Parthasarathy

Kuyel

et al. 2005

IEEE Trans. Instrum. Meas.

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113

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Abstract-Linearity testing of analog-to-digital converters (ADCs) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. This paper introduces the stimulus error identification and removal (SEIR) method for accurately testing ADC linearity using signal generators that may be significantly less linear than the device under test. In the SEIR approach, two imprecise nonlinear but functionally related excitations are applied to the ADC input to obtain two sets of ADC output data. The SEIR algorithm then uses the redundant information from the two sets of data to accurately identify the nonlinearity errors in the stimuli. The algorithm then removes the stimulus error from the ADC output data, allowing the ADC nonlinearity to be accurately measured. For a high resolution ADC, the total computation time of the SEIR algorithm is significantly less than the data acquisition time and therefore does not contribute to testing time. The new approach was experimentally validated on production test hardware with a commercial 16-bit successive approximation ADC. Integral nonlinearity test results that are well within the device specification of 2 least significant bits were obtained by using 7-bit linear input signals. This approach provides an enabling technology for cost-effective full-code testing of high precision ADCs in production test and for potential cost-effective chip-level implementation of a built-in self-test capability. Index Terms-Analog-to-digital converters (ADCs), integral nonlinearity (INL), linearity test, stimulus error identification and removal (SEIR).I. BACKGROUND T HE "histogram method" is a standard approach for quasi-static linearity testing of analog-to-digital converters (ADCs) [1]- [3]. However, during the past decade, linearity testing of ADCs has not received much research attention for several reasons. As long as best practices are followed, modern mixed-signal automated test equipment (ATE) can be used to make quasi-static linearity testing of ADCs a fairly straightforward production task for low-to-medium resolution ADCs [4]. High-precision delta-sigma ADCs are inherently sufficiently linear and do not require linearity testing. In the communications circuit area, high-speed pipelined ADCs are widely used and are usually production tested with high-frequency input signals [2], whereas quasi-static linearity testing is primarily used for debugging [5] or calibration [6]. Probably the biggest reason, however, can be attributed to the challenges associated with generating highly linear or spectrally pure test signals with no major technological breakthroughs occurring in this area in the past decade. Nevertheless, quasi-static linearity testing remains a test challenge for the production of certain classes of high performance ADCs, and the increasing downward production cost pressures are making the convenient use of expensive mixed-signal ATEs for testing low and medium resolution ADCs more difficult to justify. In this paper, emphasis ...

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Section: B Linearity Testing For Adcsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal

Jin

Parthasarathy

Kuyel

et al. 2005

IEEE Trans. Instrum. Meas.

Self Cite

113

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“…The ADC example shows that both the number of measurements and the number of arithmetic manipulations needed are manageable. Preliminary results of algorithms using this idea are presented in Parthasarathy and Geiger [2001], Parthasarathy et al [2001aParthasarathy et al [ , 2002bParthasarathy et al [ , 2003, and Jin et al [2002].…”

Section: Testing With Imprecise Stimulus and Measurementmentioning

confidence: 99%

BIST and production testing of ADCs using imprecise stimulus

Parthasarathy

Kuyel

Price

et al. 2003

ACM Trans. Des. Autom. Electron. Syst.

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A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogrambased algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n-bit ADC by using a ramp signal of much less than n-bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses (n + 3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.

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“…The static testing such as histogram, integral nonlinearlity (INL), and differential nonlinearlity (DNL) testing measures the difference between the ADC output and the ideal output. The histogram-based technique is one of the most widely used testing methods with relatively low hardware complexity [11], [12]. However, its overhead is still the primary concern.…”

Section: Introductionmentioning

confidence: 99%

Code-Width Testing-Based Compact ADC BIST Circuit

Lee

Yoo

Kim

et al. 2004

IEEE Trans. Circuits Syst. II

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This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.Index Terms-Analog-to-digital converter (ADC), built-in selftest (BIST), code width.

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A histogram based AM-BIST algorithm for ADC characterization using imprecise stimulus

Cited by 11 publications

References 5 publications

Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal

Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals With Stimulus Error Identification and Removal

BIST and production testing of ADCs using imprecise stimulus

Code-Width Testing-Based Compact ADC BIST Circuit

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