A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

Markulic, Nereo; Raczkowski, Kuba; Martens, Ewout; Filho, Pedro Emiliano Paro; Hershberg, Benjamin; Wambacq, Piet; Craninckx, Jan

doi:10.1109/jssc.2016.2596766

Cited by 56 publications

(29 citation statements)

References 31 publications

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“…There is no DTC/TDC nonlinearity calibration done in our design, but it can be applied if the spurs need further suppression in some applications. Random dithering in M [31] can also reduce part of the spurs.…”

Section: Resultsmentioning

confidence: 99%

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Zong

Chen

Staszewski

2019

IEEE J. Solid-State Circuits

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In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f 3) and thermal (1/f 2) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to 1/f 3 PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213-277-fs rms jitter in the 57.5-67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300-400 kHz.

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Section: Resultsmentioning

confidence: 99%

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Zong

Chen

Staszewski

2019

IEEE J. Solid-State Circuits

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“…The concept of a piecewise-linear DPD is aimed to reduce the complexity of the DPD and make an adaptive implementation feasible. In the context of DPLLs, an adaptive piecewise-linear DPD was originally proposed in [14] and later employed in [15,16] for the correction of the digital-to-time converter (DTC) and time-to-digital converter (TDC) nonlinearity. The general idea of the piecewise linear DPD is illustrated in Fig.…”

Section: Adaptive Digital Pre-distortionmentioning

confidence: 99%

Chirp Generators for Millimeter-Wave FMCW Radars

Cherniak

Levantino

2019

Special Topics in Information Technology

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The vast number of radar applications generates the demand for highly-linear, low-noise, fast chirp generators implemented in nanoscale CMOS technologies. Off-the-shelf chirp synthesizers are realized in BiCMOS technologies and demonstrate excellent phase noise performances, though, at high cost and limited modulation speed. This chapter describes a new class of fast and reconfigurable chirp generators based on digital bang-bang phase-locked loops, suitable for integration in modern CMOS processes. After analyzing the impact of the chirp generator impairments on a frequency-modulated continuous-wave (FMCW) radar system, a novel pre-distortion scheme for the linearization of critical blocks is introduced to achieve at the same time low phase noise and fast linear chirps. The chirp generator fabricated in 65-nm CMOS technology demonstrates above-state-of-the-art performance: It is capable of generating chirps around 23-GHz with slopes up to 173 MHz/µs and idle times of less than 200 ns with no over or undershoot after an abrupt frequency step. The circuit consuming 19.7 mA exhibits a phase noise of −100 dBc/Hz at 1 MHz offset from the carrier and a worst case in-band fractional spur level below −58 dBc. Keywords CMOS • Phase-locked loops • Radar 3.1 Introduction Cost reduction is the cornerstone in nowadays radar systems. The radar technology, which has been for a long time, since the invention in early 1930s, exclusive to military and defence, is now being adopted in a wide spectrum of applications This work has been supported by Infineon Technologies, Austria.

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“…It models the phase detector with jitter detection gain K t , the loop filter with transfer function F (s) and the VCO with transfer function K V CO /s. The phase detector is often implemented including a charge-pump (CP) [1][2][3][4][5]7]. The relation between output frequency f out and reference frequency f ref is…”

Section: Phase-locked Loopsmentioning

confidence: 99%

“…analog-to-digital converters, optical data communication and RF front-ends. Sub-sampling phase-locked loops (SSPLLs) [1][2][3][4] have superior phase noise (PN) performance compared to conventional phase-frequency detector (PFD) PLLs. However, SSPLLs only reduce the closein PN.…”

Section: Introductionmentioning

confidence: 99%

Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector

Thijssen

Klumperink

Quinlan

et al. 2018

IEEE Trans. Circuits Syst. II

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This paper presents a feedforward phase noise cancellation technique to reduce phase noise of the output clock signal of a phase-locked loop (PLL). It uses a sub-sampling phase detector to measure the phase noise and a variable time delay for cancellation. Both phase noise and spurs are reduced. Analytical expressions have been derived that characterize the performance of this technique and show its fundamental limitations. A subsampling phase-locked loop with the cancellation technique as a built-in feature is described. The feedforward technique has no stability requirements in contrast to conventional PLL architectures. The phase noise reduction bandwidth is increased to almost a third of the reference frequency-3x the maximal bandwidth for 3 rd order type-II PLLs. The proposed analytical model shows a phase noise reduction of 9 dB at a frequency offset of f ref /10. The total rms jitter is improved by 7.2 dB. The analytical results are verified by simulations.

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A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

Cited by 56 publications

References 31 publications

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Chirp Generators for Millimeter-Wave FMCW Radars

Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector

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