A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply

The tuning curve of an LC-tuned voltage-controlled oscillator (VCO) substantially deviates from the ideal curve 1/√(LC(V)) when a varactor with an abrupt C(V) characteristic is adopted and the full oscillator swing is applied directly across the varactor. The tuning curve becomes strongly dependent on the oscillator bias current. As a result, the practical tuning range is reduced and the upconverted flicker noise of the bias current dominates the 1/f3 close-in phase noise, even if the waveform symmetry has been assured. A first-order estimation of the tuning curve for MOS-varactor-tuned VCOs is provided. Based on this result, a simplified phase-noise model for double cross-coupled VCOs is derived. This model can be easily adapted to cover other LC-tuned oscillator topologies. The theoretical analyses are experimentally validated with a 0.25 μm CMOS fully integrated VCO for 5 GHz wireless LAN receivers. By eliminating the bias current generator in a second oscillator, the close-in phase noise improves by 10 dB and features -70 dBc/Hz at 10 kHz offset. The 1/f2 noise is -132 dBc/Hz at 3 MHz offset. The tuning range spans from 4.6 to 5.7 GHz (21%) and the current consumption is 2.9 mA

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This paper presents a physical derivation of phase noise in source-coupled-logic frequency dividers. This analysis takes into account both white and flicker noise sources and is verified on two 32/33 dual-modulus prescalers integrated in a 0.35-μm CMOS process. Design techniques for high-speed and low-noise operation are provided. The two integrated prescalers are identical apart from a synchronizing flip-flop at the output of one of them. The measured phase spectra are in good agreement with the estimates and demonstrate that the final synchronization allows a better trade-off between noise and power consumption. The maximum operating frequency is 3 GHz, the power consumption is 27 mW and the phase noise floor is -163 dBc/Hz referred to the 78-MHz output

The increasingly demanding performance requirements of communications systems, as well as problems posed by the continued scaling of silicon technology, present numerous challenges for the design of frequency synthesizers in modern transceivers. This book contains everything you need to know for the efficient design of frequency synthesizers for today's communications applications. If you need to optimize performance and minimize design time, you will find this book invaluable. Using an intuitive yet rigorous approach, the authors describe simple analytical methods for the design of phase locked loop (PLL) frequency synthesizers using scaled silicon CMOS and bipolar technologies. The entire design process, from system-level specification to layout, is covered comprehensively. Practical design examples are included, and implementation issues are addressed. A key problem-solving resource for practitioners in IC design, the book will also be of interest to researchers and graduate students in electrical engineering.

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In digital bang-bang phase-locked loops (BBPLLs),\ud both the hard nonlinearity of the phase detector and the frequency granularity of the digitally controlled oscillator (DCO) can give rise to undesired tones or peaking in the output spectrum. This work derives the maximum ratio between DCO resolution and jitter, which avoids limit cycles, in the case of dominant DCO noise over reference noise. Moreover, the output jitter is expressed in closed form as a function of the loop parameters and latency, revealing the existence of a minimum and suggesting an optimum design criterion. Finally, an estimation of the BBPLL output spectrum taking into account the quantization noise is provided